VDP, again

AFAIK in a standard MSX wait states are inserted in 2 places:

• In each M1 - machine cycle 1, read: one per each machine code instruction (sometimes 2 for specific groups with prefixed opcodes). This was done to support slow ROM chips, mostly unnecessary but still done so that speed is comparable across MSX models.
• In each I/O cycle (IIRC) - this is done by the Z80 itself, see timing diagrams in Z80 databook(s) for details.

In those 'some designs', are you sure wait state insertion isn't done to serve some other (internal) hw like RS232 or something like that?

It actually does not work properly at all. Writes seem do not work too. While schematic looks ok.

Problem solved. While I built up a flexible schematic to insert max 16 wait state cycles for VDP access (for very very quick CPUs) - it was not a problem. It appeared that another device on the bus was talking simultaneously, and CPU was getting stuck with vertical retrace synchronization.
@PingPong - VDP controller in this context is an addon board containing V9938 - the one which is used in MSX3.