VDP, again

By Eugeny_Brychkov

Hero (603)

Eugeny_Brychkov's picture

12-04-2011, 13:18

Hello guys, is it true that it is required to have another wait state for CPU when accessing VDP? That's not a question about VRAM access, it is about accessing VDP registers. I looked through some designs, they insert this wait state. Are there any working designs which do not insert a wait state? Thanks.

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By RetroTechie

Paladin (1008)

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13-04-2011, 17:03

AFAIK in a standard MSX wait states are inserted in 2 places:

  • In each M1 - machine cycle 1, read: one per each machine code instruction (sometimes 2 for specific groups with prefixed opcodes). This was done to support slow ROM chips, mostly unnecessary but still done so that speed is comparable across MSX models.
  • In each I/O cycle (IIRC) - this is done by the Z80 itself, see timing diagrams in Z80 databook(s) for details.

In those 'some designs', are you sure wait state insertion isn't done to serve some other (internal) hw like RS232 or something like that? Question

By Eugeny_Brychkov

Hero (603)

Eugeny_Brychkov's picture

13-04-2011, 21:07

Well, I am building VDP controller, and have an issue. It seems to write to VDP ok, but when CPU reads from VDP port (in particular - vertical retrace flag in status register 2) VDP return just FF.
If you wish we can discuss it offline, maybe you can have idea what's wrong.

By Eugeny_Brychkov

Hero (603)

Eugeny_Brychkov's picture

13-04-2011, 22:15

It actually does not work properly at all. Writes seem do not work too. While schematic looks ok.

By PingPong

Prophet (2579)

PingPong's picture

14-04-2011, 20:00

Well, I am building VDP controller, and have an issue. It seems to write to VDP ok, but when CPU reads from VDP port (in particular - vertical retrace flag in status register 2) VDP return just FF.
If you wish we can discuss it offline, maybe you can have idea what's wrong.

Hi, Eugeny!
What exaclty do you mean for "vdp controller"?

By Eugeny_Brychkov

Hero (603)

Eugeny_Brychkov's picture

14-04-2011, 22:29

Problem solved. While I built up a flexible schematic to insert max 16 wait state cycles for VDP access (for very very quick CPUs) - it was not a problem. It appeared that another device on the bus was talking simultaneously, and CPU was getting stuck with vertical retrace synchronization.
@PingPong - VDP controller in this context is an addon board containing V9938 - the one which is used in MSX3.

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