Quote:

What do you mean by ''the right spartan''?

I think he means the right type of spartan device. For each different flavor of spartan device, the tool chain needs to take into account the specifics of the device. And FPGA devices differ for example in number of logic element and the interconnect between them. The speed prediction done by the tool is based on the known physical placement & routing between these elements. Note that this differs from a logic synthesis approach for an ASIC.

@Leo: I guess that you took care to put the memory busses and video output to the pins of the spartan? This is very important, otherwise a large part of your design will be optimized away depending on the quality of the optimization... But still that does not explain this large difference, considering that you probably had the same top-level design for both devices.

@Pat: The lab name used to be PDSL indeed.

Yes I realize i was not clear.
Indeed I did a first synthesis with a wrong spartan version as target fpga and got around 35MHz.
Each time i re-run the synthesis this value varies a little, 1MHz at most.
When setting the right spartan (xc3s1000) device the frequency got much higher.
But the design has not the definitive constraints : pin positions , external clock to sdram...
An other problem is a warning that says that my frequency generated by the DCM blocks is too low :
21Mhz while minimum is 24MHz, but it is just a warning ...
An other surprise is the number of flip flops , 1000 for VDP ,only 300 for Z80, I would have said the
contrary...