Now, when OCM's VHDL code is available on the net (and some lucky people already started playing with the device), some questions about it already can be answered by just studying the code.

Here is what I've discovered from the code
(see Grauw's blog for downloading OCM CD: http://www.grauw.nl/blog/entry/385 )

1) USB is not implemented at all

2) working speeds:
-- 3.58MHz (standard speed)
-- 10.74MHz (workaround for boot failure)
(commented out) -- 21.48MHz (much troublesome with external device)

Please post your discoveries (like Grauw's note about RTC that is not saved on power off) !

Some open questions that I'd like to be answered:

1) The code was compiled using Altera's Quartus II
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition

Can we use the free web edition 6.1 instead (downloadable from Altera's site) ?

2) Will changing CPU speed change also VDP speed ?

3) There are some small tools on OCM CD with docs in Japanese.
In short, what are they all for ?

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(commented out) -- 21.48MHz (much troublesome with external device)

This could be a usefull speed with the gfx9000 and opl4.. They can handle higher bus speeds

Great !!! thanks for the vhdl code !!!!

Leo, where did you get the vhdl code?

dvik, in Grauw's blog, as I said above.

ah sorry, I missed that. I'll also download it and take a look.

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1) USB is not implemented at all

Does someone know, if the OCM is USB master or would just act as a slave device? (if someone will implement USB at all)

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2) Will changing CPU speed change also VDP speed ?

Very interesting question, as it would increase the speed in several software a LOT. But someone posted, that the VDP already works with 21Mhz, even if the Z80 runs in 3,5MHz mode. What does it mean?

Is there any persistent memory in the OCM, e.g. sram?

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Is there any persistent memory in the OCM, e.g. sram?

Isn't it possible to configure a part of the FPGA as SRAM?

So, anybody tried to compile the VHDL code himself ?

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1) USB is not implemented at all

That was known in advance .

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1) The code was compiled using Altera's Quartus II Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition

The 6.0 web edition is included on the CD.

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Isn't it possible to configure a part of the FPGA as SRAM?

Maybe, but I don’t think so.

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(commented out) -- 21.48MHz (much troublesome with external device)

Interesting, that makes sense.

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2) Will changing CPU speed change also VDP speed ?

I don’t think so, but I haven’t tested. Someone on my blog asked whether I could measure command execution speeds, I suppose I’ll have to do that.


~Grauw

I posted some on the VDP command execution speeds:

http://www.grauw.nl/blog/entry/392

Indeed, current VDP commands speed should be nice to run SymbOS and such, but at the moment even software emulators are a better choice for development (from the point of exactness of timing).

The question is whether exact VDP timing and other backward compatibility issues should be solved (at least in MSX2-compatible mode) or the upward compatibility is enough (I mean that if any existing MSX/MSX2 program runs in OCM, that's enough).

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or the upward compatibility is enough

I think upward compatibility is enough. So far MSX2, MSX2+, MSX-TR has been almost 100% backward compatible. Imo its unfortunate that the WSX and TR aren't timing compatible but thats not so important. It sounds like the OCM can't be 100% compatible with MSX2 so even in an MSX2 mode it will not behave as a real MSX2.

If the ocm would be 100% a normal msx2 in every way what would be the point of buying it.