Yes. It's more recent than the one on the OCM (from factory) itself.

Is there any versioning scheme, and how the version number of the FPGA code OCM runs can be retrieved ?

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I amp trying to compile the code for the spartan 3 witrh xilionx ise free edition but there are syntax errors in the code ! I believe the compiler from xilinx does not behaves the same way as the altera one. Of course I already replaced the altera specific device like the frequency synthesiser with a xilinxi DCM block, it is really syntaxic errors especially on arrays and type of array declaration for the opll. I may give a try disconnecting the opll ...

Leo, can you post the errormessages and the associated lines of code, if it isn't too much. Or at least one or two exemples?

Maybe the errors occur due to your use of VHDL'87 instead of VHDL'93 standard?

To answer some questions:

There is no USB chip on the board - the USB differential I/O lines are connected directly to the FPGA. This means that, in theory, either USB master or slave functionality can be added to the OCM. In practise however, I doubt that either would actually fit into the EP1C12 with the OCM - it's already 83% logic utilisation IIRC - getting close to the upper limit for 'real-world' designs without spending hundreds of hours manually fitting the design. But maybe a slave mode would fit?

Yes, FPGAs do allow instantiation of SRAM blocks. However, they're not persistent as someone suggested. IIRC the EP1C12 has around 27kB of block RAM in it. The OCM is using only 30% atm.

The input clock to the OCM is 21.48 MHz - chosen to be CPU/video-friendly. An internal PLL produces another couple of 85.92MHz clocks for the SDRAM. There are also several gated clocks used throughout the design that are derived from the 21M clock, including the CPU, which is 1/6 21M. The design changes this divisor for faster CPU speeds. The upper limit is determined by how "fast" the design can be fitted by Quartus, which depends on the complexity of the logic and the physical limitations of the EP1C12.

The VDP clock is completely independent of the cpu clock and is fixed at 21.48MHz. This is necessary because it is the base clock used for video generation and also the system clock that interleaves access to SDRAM by the CPU/VDU etc. At the very least, the CPU needs to be an integral division of the VDP clock - without a major rewrite of the design.

FWIW the bulk of the design is in the VDP and sound chips. For some reason the YM2413 is referred to as VM2413 in the source. The Z80 core is the T80 core from opencores - and it's *not* the latest version so it'll have a bug or two.

Atm I'm porting the design to my own hardware and can see the OSD on the VGA output. I'm having trouble understanding how the BIOS/BASIC ROMs are bootstrapped by the design, which has a 512-byte IPL rom embedded in the FPGA.

Hope this sheds some light.
Regards,
Mark

Interesting info tcdev, thanks for sharing it

The Japanese version of OCM have a 110/220V AC power supply like the Bazix/European version?? or only works on 110? Pardon for my English.

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The Japanese version of OCM have a 110/220V AC power supply like the Bazix/European version?? or only works on 110? Pardon for my English.

The Japanese version has a universal (100-240V, 50/60Hz) power supply. Though, it comes with a Japanese plug. In Europe you must use an adapter plug to plug it into the socket. Don't know about countries in other parts of the world.

Thanks Alex.

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Atm I'm porting the design to my own hardware and can see the OSD on the VGA output. I'm having trouble understanding how the BIOS/BASIC ROMs are bootstrapped by the design, which has a 512-byte IPL rom embedded in the FPGA.

I'm busy myself porting the thing to my old Altera-Apex development board. I allready have it running, without having to modify the IPL rom. But because I was curious wat it does, I disassembled it and had a look at it. Although I have quite some Z80 experience I did not succeed in understanding it within the time I was willing to spend at that moment. But maybe you are interested in the disassembled code (including assembler to reproduce the exact same binary):

http://home.versatel.nl/timmarianne/ipl_rom.zip

For those wondering: the adapter with the OCM can be used in USA, UK and JP. The Bazix edition contains an extra adapter allowing you to use it in most/all European countries as well.

timbr,
as you can see, tcdev's "clone" is already running, and he wrote a document that describes porting steps - in this topic.
Can you comment and add something to his work ?

Timbr,

So do you have the BIOS booting too? Which Apex dev board do you have? I have an old one myself, but I can't recall which device I have on it (could be an ACEX?) - I didn't think to try because I assumed it was too small for the design?

I disassembled the code in IDA and have identified the routine that reads from the EPCS device. I got hints from the PLDLOAD/PLDSAVE source code in the CD image .RAR file I downloaded from Laurens' blog page.

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Timbr, So do you have the BIOS booting too? Which Apex dev board do you have? I have an old one myself, but I can't recall which device I have on it (could be an ACEX?) - I didn't think to try because I assumed it was too small for the design? I disassembled the code in IDA and have identified the routine that reads from the EPCS device. I got hints from the PLDLOAD/PLDSAVE source code in the CD image .RAR file I downloaded from Laurens' blog page.

Yes, I also have it running, see post on http://www.msx.org/forumtopicl7056.html. It is a Apex 20K200 (8320 LE's).
I had a different approach. I removed the IPL rom and wrote something myself. Also I do the flash->ram copy in a total different way. I have 2MB SRAM on the board instead of SD-RAM. I made a 'dual port SRAM controller with synchronous interface'. This controller also takes care of copying my parallel flash to the SRAM at power up. So in software, there is not much left to do for the IPL rom. Basically the only thing he has to do is set the VDP pallette to the correct values.
I rewrote the top-level to use a T80 with synchronous interface (t80se) instead of the asynchronous t80a. The result is that I can now run at 21MHz without any waitstates on memory access, and it compiles without timing analyser violations.

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For some reason the YM2413 is referred to as VM2413 in the source.

'VM2413' is a name of VHDL implementation of YM2413 (use google>'VM2413' to get more info).