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Ok then, the Z80/R800 has those useful instructions called EX and EXX. With those really fast instructions (1 t-state) you can in total address eight 16-bit registers (and I read the exx-es on the Z380 were really slow, 3 t-states? then you'd better not use them often).

Still faster than push/pop/ld from memory.

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Since you already said that that was the max register usage... Also from my own experience, only few routines need more registers than I have available, and those are usually not the critical ones inside loops, which matter most cuz they get repeated often. So in effect the additional registers are easy, probably offer a tiny bit faster code, but no significant advantage, speed-wise.

Somehow I always need more registers... And that '8 reg max' is based on a old bullshit study.

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R800 is definately 16-bit, it's the ALU's reach that matters, *not* the external interface, and the ALU handles everything on a 16-bit level. If it didn't, there wouldn't even be a single base of reasoning to claim it's a 16-bit processor (which they did).

I do not care about alu-sizes, external interfaces or whatever. Everything about r800 feels 8 bit. As I said: I see why GuyveR800 (and many others, ofcourse) says R800 is 16 bit. I remember Sega going: 'Dreamcast is 128-bit.' Right.

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About RISC, I don't know the exact details about it, but afaik the ARM is one of the ultimate examples of a RISC processor, ne?

Far from it.

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Or at least a very cool, commonly used one. Ok, I know the ARM .

8)

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Does the THUMB mode of the ARM processor make it any less RISC? Just think of the R800 as an ARM continuously running in THUMB mode ^_^.

Of course thumb does make it less risc. And all that shifting doesn't help either. Having said that, I like ARM. It is a nice example of a combination of risc and cisc.

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Everything about r800 feels 8 bit. As I said: I see why GuyveR800 (and many others, ofcourse) says R800 is 16 bit.

You haven't felt the R800 at all, so how can you say it... To me everything about the R800 feels 16 bit. The 16-bit instructions take just one cycle, that's all the proof anyone would need.

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Far from it.

Name the processor that you think is the ultimate example of RISC technology then. And please name one that actually exists.

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Having said that, I like ARM. It is a nice example of a combination of risc and cisc.

LOL, incredible... I wonder if there are more people like you. Do you guys have a special meeting place?

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You haven't felt the R800 at all, so how can you say it...

Hwehe I never even felt a Z80...

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To me everything about the R800 feels 16 bit. The 16-bit instructions take just one cycle, that's all the proof anyone would need.

I know of some 64-bit cpu design that takes 2 cycles to add two 64 bit-numbers, still I think it's 64 bit...
How many bits is a Z80? It takes more than one cycle to finish a 8-bit instruction. A Z80 is 2-bit then?

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Name the processor that you think is the ultimate example of RISC technology then. And please name one that actually exists.

Sparc, mips. The first designs looked very risc. The first sparcs didn't even have a mul-instruction. Not ultimate but, 'ultimater' (hahaha) than arm... Hoever, I expect you to disagree with me here anyway, whatever cpu I name. Futhermore, as you said yourself, RISC is no technology but just a set of ideas...

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LOL, incredible... I wonder if there are more people like you. Do you guys have a special meeting place?

Me too. It is lonely down here.

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>>To me everything about the R800 feels 16 bit. The 16-bit instructions take just one cycle, that's all the proof anyone would need.<<I know of some 64-bit cpu design that takes 2 cycles to add two 64 bit-numbers, still I think it's 64 bit... How many bits is a Z80? It takes more than one cycle to finish a 8-bit instruction. A Z80 is 2-bit then?

You are confusing RISC and CISC architectures here Z80 is CISC so indeed it takes more than one cycle to finish an instruction. R800 however.....
Are you beginning to get the point now?

BTW, when talking about Z80 M-cycles (not T-states), 8 bit instructions generally take 1 M-cycle and 16 bit instructions 2 M-cycles.

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----------------------- I know of some 64-bit cpu design that takes 2 cycles to add two 64 bit-numbers, still I think it's 64 bit... How many bits is a Z80? It takes more than one cycle to finish a 8-bit instruction. A Z80 is 2-bit then? --------------------------- You are confusing RISC and CISC architectures here Z80 is CISC so indeed it takes more than one cycle to finish an instruction. R800 however..... Are you beginning to get the point now? BTW, when talking about Z80 M-cycles (not T-states), 8 bit instructions generally take 1 M-cycle and 16 bit instructions 2 M-cycles.

Uhm, I do not think I confuse RISC and CISC here. (Or am I really lost? ) And I am getting your point...
That 64-bit design is also RISC-based, still it takes 2 M-cycles for most (if not all) 64-bit instructions. Worse: one instruction takes about 7 cycles, iirc.
And a pipelined cisc cpu should be able to finish a instruction each cycle. (Sounds almost like a r800 ) If I understand you correctly, you are practically saying a R800 is faster than a 68000? And isn't it strange that Zilog didn't make the Z380 more Risc-like?

You do seem lost ^^; And I don't see where you get 68000 vs R800 remark from.
You're contradicting yourself quite heavily now, claiming that the (apparently nameless) 64-bit design is RISC-based, while it obviously doesn't match your previously set 'must-haves' for a processor to be called RISC-based.

Furthermore, how deep a pipeline do you think R800 has? I'm not at all convinced it has a pipe at all... It would've come up in at least some marketing or technical articles. Z380 isn't pipelined either, it just has a prefetch buffer. And don't ask me why Z380 isn't more RISC-like, because ZiLOG hasn't made RISC-like Z80 designs either, even though several other companies (Toshiba, Rabbit, AB, to name a few) have.

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You do seem lost ^^;

Not from where I stand.

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And I don't see where you get 68000 vs R800 remark from.

Just a question. I always thought a Amiga was faster than a Turbo R.

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You're contradicting yourself quite heavily now, claiming that the (apparently nameless) 64-bit design is RISC-based, while it obviously doesn't match your previously set 'must-haves' for a processor to be called RISC-based.

It matches all my 'must-haves', unfortunately even the 'R0-reads-as-zero' 'must-have'. And what's in a name anyway?

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Furthermore, how deep a pipeline do you think R800 has? I'm not at all convinced it has a pipe at all... It would've come up in at least some marketing or technical articles.

Yes, I am clearly lost here. How does it execute a instruction per cycle without a pipeline?

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Z380 isn't pipelined either, it just has a prefetch buffer.

'Instruction fetch/execution overlap' looks like a pipeline to me...

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And don't ask me why Z380 isn't more RISC-like, because ZiLOG hasn't made RISC-like Z80 designs either, even though several other companies (Toshiba, Rabbit, AB, to name a few) have.

Zilog made the z800 or z8000 or whatever z8<add some zeros> it was, so they have some risc experience. I think it's strange it wasn't used for the z380, that's all...

You're beginning to sound ridiculous now...
I never said anything about Amiga vs MSX or 68000 vs R800 in this thread, so I don't know how you came up with that.
Furthermore you're not answering questions, just countering them with irrelevant other questions.
And you seem to have a very WIDE definition of pipelines.

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You're beginning to sound ridiculous now...

You did a long time ago...

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I never said anything about Amiga vs MSX or 68000 vs R800 in this thread, so I don't know how you came up with that.

Do you even read what I say? Years ago I thought a 68000 was faster than a R800. But now, R800 being RISC and all, I am not that certain anymore. Thought you may know the answer...

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Furthermore you're not answering questions, just countering them with irrelevant other questions.

What were your questions again? And asking how a R800 is capable of executing a instruction in one cycle without pipeline is not irrelevant... I do not know any other method of finishing a instruction every cycle.

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And you seem to have a very WIDE definition of pipelines.

So?

Ok, I think it's about time to wrap this discussion up... conclusions?

- There is no 'pure' RISC processor as of yet, so actually no processor can be called RISC for that matter. However, a processor can be RISC-based. Depending on your standards, the R800 is RISC-based. (or not)
- From the experience of at least one coder who has experience with optimized coding for both the R800 and the Z380 we can conclude that the one-instruction-per-cycle setup of the R800 generally results in a relatively larger speed-gain than the advantage of a 16-bit Z380 running on a higher clock. Some instructions are indeed a lot faster than on a R800 but in practical situations the R800 still wins... most of the time.
- The R800 can handle 16 bit numbers. It has 16 bit registers, a 16 bit ALU, has 16 bit adressing space yet is connected to an 8 bit databus. To me, that makes it a 16 bit processor. A Ferrari engine in a Trabant still makes it a Ferrari engine.

I think both GuyveR and sjoerd have said what they had to say on this subject. Instead of going round in circles and pointing to things already said before I think it's best to see if other people have something to say about this.

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Ok, I think it's about time to wrap this discussion up... conclusions?

I do not seem to come to the same conclusions Stange enough...

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- There is no 'pure' RISC processor as of yet, so actually no processor can be called RISC for that matter. However, a processor can be RISC-based. Depending on your standards, the R800 is RISC-based. (or not)

There probably never will be a pure risc cpu, the cisc versus risc debate is over; cisc won. I am wondering how the R800 executes a instruction every cycle without a pipeline...

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- From the experience of at least one coder who has experience with optimized coding for both the R800 and the Z380 we can conclude that the one-instruction-per-cycle setup of the R800 generally results in a relatively larger speed-gain than the advantage of a 16-bit Z380 running on a higher clock. Some instructions are indeed a lot faster than on a R800 but in practical situations the R800 still wins... most of the time.

According to GuyveR800: R800 at 7MHz is as fast as a Z380 at 14MHz. The Z380 is faster when using mul/div instructions.
And I am not convinced that Z80+Z380 is slower than just a Z80.

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- The R800 can handle 16 bit numbers. It has 16 bit registers, a 16 bit ALU, has 16 bit adressing space yet is connected to an 8 bit databus. To me, that makes it a 16 bit processor. A Ferrari engine in a Trabant still makes it a Ferrari engine.

That makes it a wasted ferrari engine...

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I think both GuyveR and sjoerd have said what they had to say on this subject. Instead of going round in circles and pointing to things already said before I think it's best to see if other people have something to say about this.

Asking about that pipeline thing is not running in circles...