detect the vdp refresh speed (50hz or 60hz) on a MSX1:
actually i use a void loop and i count the jiffy increments before and after the loop. But i'm looking for a more elegant solution . Any idea?
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detect the vdp refresh speed (50hz or 60hz) on a MSX1:
actually i use a void loop and i count the jiffy increments before and after the loop. But i'm looking for a more elegant solution . Any idea?
ld a,(2Bh) And then it is one of the 8 bits 
bit 7 I think...
Right, bit 7, 0=60Hz & 1=50Hz
thx, a lot!!!!!!!!!!!!!!!!!!!!!!!!
euh, that only works when MSX BIOS is enabled (in page 0) and VDP change has been made via BIOS call. (or if the user updates 0x2B when changing VDP regs)
And it won't be reliable in MSX1 machines with MSX1 BIOS installed and featuring V9938 VDP, such as SVI738 and Yamaha CMX5II/128. For these machines, first you should detect them and then read the corresponding VDP register.
Reading the BIOS byte, you'll only know the default retrace frequency. That's OK if it cannot be changed (TMS99xx). If it can be changed, then you'll have to make a guess
my prev post was a bit fuzzy (aah, whatsinnaname)
VDP regs update to vars is not stored in 2B ofcourse but in VDP buf in Hi-Mem.
2B is initial (default) startup and machine type /BIOS settings.
Basic ROM version
here's an excerpt from MAP: (http://map.tni.nl/resources/msxsystemvars.php)
7 6 5 4 3 2 1 0
| | | | +-+-+-+-- Character set
| | | | 0 = Japanese, 1 = International, 2=Korean
| +-+-+---------- Date format
| 0 = Y-M-D, 1 = M-D-Y, 2 = D-M-Y
+---------------- Default interrupt frequency
0 = 60Hz, 1 = 50Hz
Here's where the BIOS calls and BASIC store any VDP changes (reg 0 till 7 + stat):
#F3DF-#F3E7
I will stay to the old solution: delay loop of 1 second (all msx1 have z80 @3.58Mhz) and count of nints....
Here is the one I wrote and have been using in several games and demos:
;;
;; returns 1 in a and clears z flag if vdp is 60Hz
;;
CheckIf60Hz:
di
in a,($99)
nop
nop
nop
vdpSync:
in a,($99)
and 0x80
jr z,vdpSync
ld hl,$900
vdpLoop:
dec hl
ld a,h
or l
jr nz,vdpLoop
in a,($99)
rlca
and 1
ei
ret
The code starts with syncing to vblank. Then the vdpLoop pretty much loops for around 290 scanlines. If the vblank bit is set after the loop finishes it means that more than one frame has passed (60Hz).
The code starts with syncing to vblank. Then the vdpLoop pretty much loops for around 290 scanlines. If the vblank bit is set after the loop finishes it means that more than one frame has passed (60Hz).
thx dvik, this is similar to mine.
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