OCM-PLD Pack 2.3

por KdL en 13-04-2010, 10:46
Tema: MSX Revival
Idiomas:

A new version of KdL's 1chipMSX firmware has been released, a practical - if not essential - update for 1chipMSX'es. New in this version:

  • Fixed a bug inside of "vm2413.vhd" source code
  • Modified DIP-SW4 original function with 2MB/4MB memory mapper selection
  • There is a separated PLD file for every keyboard layout; these files have been optimized with Quartus II 9.1sp2 Wed Edition
  • Updated DIP-SW User Manual [esemsx3\src\doc\dipsw_v23.htm]
  • This package will have the full source code from now

A tip: to bypass the error messages of MSXDOS2 when drive B: of the MegaSD is empty, make an ASSIGN B:=A: at the prompt of the command line.

Relevant link: KdL's page

Comentarios (16)

Por Grauw

Ascended (8612)

Imagen del Grauw

13-04-2010, 19:09

Nice!

Por spl

Paragon (1461)

Imagen del spl

14-04-2010, 18:38

Nice!!! Big smile

Por ant0niutti

Master (159)

Imagen del ant0niutti

14-04-2010, 23:42

Good job!
Big smile

Por sd_snatcher

Prophet (3134)

Imagen del sd_snatcher

15-04-2010, 00:25

Very welcome news! Thanks for your effort!

Por doraemonppc

Master (245)

Imagen del doraemonppc

15-04-2010, 00:39

A lot of thanks!

Por Atheus

Expert (73)

Imagen del Atheus

19-04-2010, 22:44

Thanks a lot KdL !

For french users, an AZERTY version of this pack is available here :
http://www.atheus.fr/index.php?page=ocm

Have fun with it !

Por KdL

Paragon (1253)

Imagen del KdL

26-04-2010, 02:01

Hi all! Smile

A note to obtain a correct PLD file from a clean and uncompiled project of Quartus II 9.1sp2 Web Edition:

1. run [c:\altera\esemsx3\emsx_top.qpf] to load project
2. start compilation for a 1st pass (wait for done)
3. start compilation for a 2nd pass (wait for done)
4. go to create emsx_top.pof and emsx_top.pld files

I don't know why but the PLD obtained from 1st pass isn't equal to that of next passes.
Probably it will not be optimized. Question

Por KdL

Paragon (1253)

Imagen del KdL

27-04-2010, 05:56

I confirm!
To optimize design (and PLD) you can use Quartus II Design Space Explorer.

These are the best results for v2.3uk:

+-----------------------------------------------------------------------------+
| Settings for Point 9 (Best)                                                 |
+-----------------------------------------------------------------------------+
+----------------------------------------------+------------------------------------------------------------------------------+--------------+
| Setting                                      | New Value                                                                    | Base Value   |
+----------------------------------------------+------------------------------------------------------------------------------+--------------+
| CYCLONE_OPTIMIZATION_TECHNIQUE               | BALANCED                                                                     | AREA         |
| PHYSICAL_SYNTHESIS_REGISTER_RETIMING         | ON                                                                           | ON           |
| SEED                                         | 1                                                                            | 1            |
| STATE_MACHINE_PROCESSING                     | AUTO                                                                         | AUTO         |
| MUX_RESTRUCTURE                              | OFF                                                                          | AUTO         |
| PHYSICAL_SYNTHESIS_COMBO_LOGIC               | ON                                                                           | ON           |
| FITTER_EFFORT                                | STANDARD FIT                                                                 | STANDARD FIT |
| PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION      | ON                                                                           | ON           |
| ROUTER_TIMING_OPTIMIZATION_LEVEL             | MAXIMUM                                                                      | NORMAL       |
| ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION | AUTO                                                                         | AUTO         |
| PRE_MAPPING_RESYNTHESIS                      | OFF                                                                          | OFF          |
| PHYSICAL_SYNTHESIS_EFFORT                    | EXTRA                                                                        | EXTRA        |
| PLACEMENT_EFFORT_MULTIPLIER                  | 1.0                                                                          | 1.0          |
| -setup-script                                | quartus_cdb:c:/altera/91sp2/quartus/common/tcl/packages/dse/llr_softener.tcl |              |
+----------------------------------------------+------------------------------------------------------------------------------+--------------+


+------------------------------------------------------------------------+
| QSF Setting                                                            |
+------------------------------------------------------------------------+
| set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED    |
| set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON    |
| set_global_assignment -name STATE_MACHINE_PROCESSING AUTO              |
| set_global_assignment -name MUX_RESTRUCTURE OFF                        |
| set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON |
| set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM   |
| set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF                |
| set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON          |
| set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA            |
| set_global_assignment -name FITTER_EFFORT "STANDARD FIT"               |
+------------------------------------------------------------------------+


+-----------------------------------------------------------------------------+
| Results for Point 9 (Best)                                                  |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------------+---------------------------------------------------------------------+
| All Clock Hold Failing Paths                                         | 0                                                                   |
| All Clock Recovery Failing Paths                                     | 0                                                                   |
| All Clock Removal Failing Paths                                      | 0                                                                   |
| All Clock Setup Failing Paths                                        | 1261                                                                |
| All Failing Paths                                                    | 1261                                                                |
| Average Slack for Failing Paths                                      | -1.988                                                              |
| Clock Hold: 'PLL4X:U00|altpll:altpll_component|_clk0': Actual Time   | unknown                                                             |
| Clock Hold: 'PLL4X:U00|altpll:altpll_component|_clk0': Failed Paths  | 0                                                                   |
| Clock Hold: 'PLL4X:U00|altpll:altpll_component|_clk0': Slack         | 0.822 ns                                                            |
| Clock Hold: 'PLL4X:U00|altpll:altpll_component|_clk1': Actual Time   | unknown                                                             |
| Clock Hold: 'PLL4X:U00|altpll:altpll_component|_clk1': Failed Paths  | 0                                                                   |
| Clock Hold: 'PLL4X:U00|altpll:altpll_component|_clk1': Slack         | 1.044 ns                                                            |
| Clock Hold: 'pSltClk': Actual Time                                   | unknown                                                             |
| Clock Hold: 'pSltClk': Failed Paths                                  | 0                                                                   |
| Clock Hold: 'pSltClk': Slack                                         | 0.822 ns                                                            |
| Clock Period: Geometric Mean                                         | 32.19 ns                                                            |
| Clock Setup: 'PLL4X:U00|altpll:altpll_component|_clk0': Actual Time  | unknown                                                             |
| Clock Setup: 'PLL4X:U00|altpll:altpll_component|_clk0': Failed Paths | 896                                                                 |
| Clock Setup: 'PLL4X:U00|altpll:altpll_component|_clk0': Slack        | -9.575 ns                                                           |
| Clock Setup: 'PLL4X:U00|altpll:altpll_component|_clk1': Actual Time  | unknown                                                             |
| Clock Setup: 'PLL4X:U00|altpll:altpll_component|_clk1': Failed Paths | 365                                                                 |
| Clock Setup: 'PLL4X:U00|altpll:altpll_component|_clk1': Slack        | -10.812 ns                                                          |
| Clock Setup: 'pSltClk': Actual Time                                  | 32.186 ns                                                           |
| Clock Setup: 'pSltClk': Failed Paths                                 | 0                                                                   |
| Clock Setup: 'pSltClk': Slack                                        | 123.571 ns                                                          |
| Elapsed Time: Analysis & Synthesis                                   | 00:01:48                                                            |
| Elapsed Time: Assembler                                              | 00:00:02                                                            |
| Elapsed Time: Classic Timing Analyzer                                | 00:00:13                                                            |
| Elapsed Time: Fitter                                                 | 00:01:58                                                            |
| Elapsed Time: Total                                                  | 00:04:01                                                            |
| Quality of Fit                                                       | -18.70918125                                                        |
| Total block memory bits                                              | unknown                                                             |
| Total logic elements                                                 | 11979                                                               |
| Total Thermal Power Dissipation                                      | unknown                                                             |
| Worst-case Slack                                                     | -10.812 ns (Clock Slack: 'PLL4X:U00|altpll:altpll_component|_clk1') |
| Worst-case tco: Actual Time                                          | 26.173 ns                                                           |
| Worst-case tco: Failed Paths                                         | 0                                                                   |
| Worst-case tco: Slack                                                | unknown                                                             |
| Worst-case th: Actual Time                                           | -2.897 ns                                                           |
| Worst-case th: Failed Paths                                          | 0                                                                   |
| Worst-case th: Slack                                                 | unknown                                                             |
| Worst-case tsu: Actual Time                                          | 12.289 ns                                                           |
| Worst-case tsu: Failed Paths                                         | 0                                                                   |
| Worst-case tsu: Slack                                                | unknown                                                             |
+----------------------------------------------------------------------+---------------------------------------------------------------------+

Fitter Status : Successful - Tue Apr 27 04:40:36 2010
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : emsx_top
Top-level Entity Name : emsx_top
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Total logic elements : 11,979 / 12,060 ( 99 % )
Total pins : 171 / 173 ( 99 % )
Total virtual pins : 0
Total memory bits : 54,456 / 239,616 ( 23 % )
Total PLLs : 1 / 2 ( 50 % )

Por KdL

Paragon (1253)

Imagen del KdL

27-04-2010, 06:14

a bug?
RCA audio output is not very clean when vga cable is connected;
you can detach vga cable to hear the difference oOoOoO

mmh... I will study if exist a solution to apply for next update. Smile

Por Atheus

Expert (73)

Imagen del Atheus

27-04-2010, 20:38

Thx KdL for your work ...
Try to compile a new Azerty mapping ...

Por KdL

Paragon (1253)

Imagen del KdL

28-04-2010, 08:41

I don't have an Azerty keyboard here and I don't have your source code... which is the problem?

Por KdL

Paragon (1253)

Imagen del KdL

28-04-2010, 17:39

Simple test of audio noise:

VGA cable noise is very low with my LCD display and very high with CRT display.
A conclusion is that an external filter is necessary to remove it because 1chipMSX have none.
I advise to use a LCD display.

Por Atheus

Expert (73)

Imagen del Atheus

28-04-2010, 20:45

No problem, azerty mapping is working.

Por KdL

Paragon (1253)

Imagen del KdL

08-07-2010, 19:31

QUARTUS II v10.0 is out... but and "Internal Error" is occurred with 1chipMSX sources... Crying Crying Crying

https://www.altera.com/download/software/quartus-ii-we

Por KdL

Paragon (1253)

Imagen del KdL

09-08-2010, 02:53

I added the spoiler on the next features of OCM-PLD PACK v2.4 in my homepage …stay tuned! Hannibal

Link: http://www.webalice.it/gnogni/

Por KdL

Paragon (1253)

Imagen del KdL

10-08-2010, 00:37

QUARTUS II v10.0rev2 is out... I go to try it !!

LOL!