code:
-- SuperTurbo
-- Copyright (c) 2014 Fabio Belavenuto
-- Implementa o circuito do SuperTurbo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity superturbo is
port (
reset_n : in std_logic; -- Entrada /RESET
clockTurbo : in std_logic; -- Entrada clock 10.7MHz
clockNormal : in std_logic; -- Entrada clock 3.57MHz
slow : in std_logic; -- Se '0' solta clock normal
turboon : out std_logic; -- Informacao se Turbo esta ativado
clockout : out std_logic -- Saida clock CPU
);
end entity;
architecture Behavioral of superturbo is
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal q : std_logic_vector(1 downto 0) := "11";
begin
-- Controle do chaveamento dos clocks
process(reset_n, clkout1)
variable cntslw : integer range 0 to 31 := 0;
variable slow2 : std_logic := '1';
begin
if reset_n = '0' then
q <= "00";
cntslw := 0;
slow2 := '1';
elsif rising_edge(clkout1) then
if slow = '1' then
if cntslw < 31 then
cntslw := cntslw + 1;
else
slow2 := slow;
end if;
else
cntslw := 0;
slow2 := slow;
end if;
q(1) <= slow2;
q(0) <= q(1);
end if;
end process;
clkout1 <= clockNormal when q(1) = '0' else clockTurbo;
with q select
clkout2 <=
clockNormal when "00",
clockTurbo when "11",
'1' when others;
Producing and open source!! this is amazing! You have just earned my respect.
One more question. Does the CPU brake in clockspeed when accessing VDP or does it use some kind of wait state? Will the PSG run stable in a certain pitch or will it pitch variably like the 7Mhz mods?