Yamaha CX5M, CX5M II, CX7M

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Por zPasi

Champion (499)

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22-11-2015, 16:18

Grauw wrote:
zPasi wrote:

Do typical (not BASIC) games even care about the BIOS?

Yes.

Heh. I just checked with Space Manbow: it doesn't seem to care about the MSX2 BIOS. Of course it doesn't really work with only 16K of VRAM, but when I press the space key, the game begins. It shows the incomplete background and sprites, plays music and even scrolls the background!

So, at least for this game upgrading the VRAM should be enough. Of course, if converting to MSX2, it probably should be done properly or not at all.

Por sd_snatcher

Prophet (3505)

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22-11-2015, 18:43

Except for a minor flop in the PSG routines, Space Manbow (like all Konami games after 1985) exclusively uses the BIOS to access the MSX hardware. Except for this bug to access the PSG, it passes the Acid2Test.

Por zPasi

Champion (499)

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23-11-2015, 09:05

sd_snatcher wrote:

Except for a minor flop in the PSG routines, Space Manbow (like all Konami games after 1985) exclusively uses the BIOS to access the MSX hardware.

It doesn't use BIOS to check if the machine is really an MSX2, nor accessing the VDP.

"Please note that legal VDP direct I/O will not fail."

Por l_oliveira

Hero (533)

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23-11-2015, 19:29

zPasi wrote:
Grauw wrote:
zPasi wrote:

Do typical (not BASIC) games even care about the BIOS?

Yes.

Heh. I just checked with Space Manbow: it doesn't seem to care about the MSX2 BIOS. Of course it doesn't really work with only 16K of VRAM, but when I press the space key, the game begins. It shows the incomplete background and sprites, plays music and even scrolls the background!

So, at least for this game upgrading the VRAM should be enough. Of course, if converting to MSX2, it probably should be done properly or not at all.

Try Aleste. That one WORKS FULLY on a MSX1 ROM.

Por zPasi

Champion (499)

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06-12-2015, 11:34

I opened the machine. It is XB300 board version, so this is the right MSX2 conversion document.

Those 64K x 4 DRAM chips doesn't seem to be generally available anymore, so this gets a little tricky. I seem to have three options here:

1) to buy "old new stock" chips from eBay or something
2) to adapt an SRAM somehow
3) to cannibalize the 128K main memory and replace that with (probably larger) SRAM (or SIM / DIMM) based mapper.

The problem with option 2 is that SRAMs don't have that row / column addressing scheme, so I'd need some latch chips to handle that, but it doesn't sound too hard. Has anyone tried something like that?

Por RetroTechie

Paragon (1563)

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06-12-2015, 21:09

zPasi wrote:

The problem with option 2 is that SRAMs don't have that row / column addressing scheme, so I'd need some latch chips to handle that, but it doesn't sound too hard. Has anyone tried something like that?

I give it a good chance that this would work, provided you use fast enough SRAM/register/inverter. But I don't know if anyone ever tried that with a V9938. Timing diagrams for V9938 VRAM access are in its databook.

Problem here is that the V9938 uses 2 /CAS signals, meaning that (using above construct) you'd need 2 SRAMs. Kind of silly when a single 128Kx8 SRAM would be a nice fit. The alternative is figure out how to somehow use a single SRAM. Which (given the timing restraints) I think wouldn't be easy - perhaps would need a high speed (cache) SRAM.

So for simplicity sake I'd go for the "source some 4464's" option. They shouldn't be too hard to find (and yes, taking from main RAM is an option).

Por zPasi

Champion (499)

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07-12-2015, 09:18

Thanks!

RetroTechie wrote:

Problem here is that the V9938 uses 2 /CAS signals, meaning that (using above construct) you'd need 2 SRAMs. Kind of silly when a single 128Kx8 SRAM would be a nice fit.

A flip-flop to SRAM A16 could do it. But the whole thing is more complicated than I thought, indeed.

RetroTechie wrote:

So for simplicity sake I'd go for the "source some 4464's" option. They shouldn't be too hard to find (and yes, taking from main RAM is an option).

I think I'll just do that.

Por RetroTechie

Paragon (1563)

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07-12-2015, 16:26

RetroTechie wrote:

But I don't know if anyone ever tried that with a V9938

Looks like some people have:
Is the V9938 compatible with SRAM ?
LC64 - a modular PLCC 6502 computer: V9938 DRAM problems

Por zPasi

Champion (499)

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08-12-2015, 14:51

RetroTechie wrote:
RetroTechie wrote:

But I don't know if anyone ever tried that with a V9938

Looks like some people have:
Is the V9938 compatible with SRAM ?
LC64 - a modular PLCC 6502 computer: V9938 DRAM problems

Ok. There is this schema on that "Is the V9938 compatible with SRAM" thread. How simple! I had trouble understanding that at first, but I think it makes sense after all.

When RAS goes low, the 373 stores the upper address bits. Then the V9938 feeds the lower a-bits, but the value in 373 doesn't change. At the same time, RAS activates the SRAM. The CAS signal isn't used to anything, except to select which half of the 128K memory is to be accessed. Only one CAS line is needed for that, and it doesn't matter which of the two.

Did I get it right?

Por tvalenca

Paladin (747)

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08-12-2015, 18:42

RetroTechie wrote:

Problem here is that the V9938 uses 2 /CAS signals, meaning that (using above construct) you'd need 2 SRAMs. Kind of silly when a single 128Kx8 SRAM would be a nice fit. The alternative is figure out how to somehow use a single SRAM. Which (given the timing restraints) I think wouldn't be easy - perhaps would need a high speed (cache) SRAM.

Actually, if you get a fast enough AND port (not NAND, or even faster like a modern CPLD) it would be possible to use just one 128k SRAM. Wire both /CAS signals to a *FAST* *AND* port so either falling /CAS signal will activate the SRAM. Then wire one of the /CAS signals to the last bit available on the SRAM addresss bus (you already wired A0-A15 to AD0-7 from VDP, half of them through a latch) so you have each byte of the 128k SRAM addressed.

Well... I'm not sure right now which refresh method the VDP uses. If it uses some kind of CAS refresh and both /CAS signals fall at the same time during refresh, you may need to XOR both /CAS signals instead and wire the output through an inverter to /OE, then the SRAM will only be active when /CAS0 and /CAS1 have different values. Then, you still wire one of the /CAS signals to address bus of the SRAM and latch half of them.

I haven't tested either of these layouts, but either one should work.

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