Over last several weeks I had been scratching my head over the prototyping of the new encoder board for MSX. It is based on AD725ARZ chip. However prototyping does not go smooth, and I am still to decide if I dtop AD725 and reuse my old good CXA1645 design.
I was aiming high:
- design must have S-video as well as color composite outputs;
- must output good quality of composite signal;
- should work in both NTSC and PAL modes.
Some days ago I learnt that Alexey did already make an attempt to use AD725 before - his device is called Zefisha. I do think that he turned back to CXA1645 for the reason... Here're the issues I found out during development:
- AD725's RGB signals are max 0.741 Vpp. V99xx outputs signals max of 1 Vpp. While AD725 can cope with level above spec, I would say the picture is a kind of over-saturated, and in addition it is not clear is this overvoltage causes excessive power consumption or may cause premature damage to the chip. I was advised to use buffer chips, but I think that is not so simple as well as adds cost and board space;
- AD725 is very critical to the width of the HSYNC pulse. The issue described here costed me quite a time and effort to find root cause for. While VDP datasheet promises max 4.7 us for HSYNC pulse, it may be up to 5.something at the CSYNC output, and delayed/increased in time down the circuit. In my case CSYNC pulse was 6 us, and AD725 was going crazy;
- The worst issue with AD725 is dot crawl over composite signal. Tuning 14.31818 MHz oscillator to the frequency stops dot crawl, but there're still color artifacts on the screen. Interesting, I do not recall having such issues with CXA1645 - its image is a little worse than AD725, but does not exhibit these dynamic issues. Tried to clean up power to no positive outcome. Generally dot crawl happens because there's carrier phase misalignment between horizontal lines. I have thought of various ways to align the clock to the CSYNC pulse (to ensure clock is always aligned and not drifts away with temperature), and decided that it would be an overkill in terms of components and cost. In addition, VDP consumes 21.47727 MHz clock (6*NTSC), but AD725 wants 14.31818 MHz (4*NTSC), and the only operation of division by 1.5 to sync AD725 with V99xx adds several chips. If using CXA1645 I connect it directly to the CPUCLK of NTSC frequency.
You may ask why I use AD725 and not 24/23 which accept CPUCLK. Answer is simple: I thought that higher frequency will lead to better quality, and I simply did not find those chips available.
We had been testing with edoz yesterday on his PAL machines both NTSC and PAL modes, and 8280 cool monster he possessed appeared to be really cool machine. I looked into its circuit diagram, and while did not understand how it works, it seems it is capable of changing VDP frequency depending on the encoding mode selected. I also suspect that it has custom BIOS to set F7 register together with VDP register #9. Anyway I am not going to implement anything like this as it is real overkill, as well as Sony V70xx chipset most probably is not available any more.

