BitBuster depack in VRAM

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By ARTRAG

Enlighted (5824)

ARTRAG's picture

19-02-2008, 14:04

hi metalion, no release jet?

By Metalion

Paladin (909)

Metalion's picture

19-02-2008, 19:56

hi metalion, no release jet?

Here are the first releases.
Those are the VRAM depackers working up to $3FFF in VRAM (MSX1 and MSX2).
The code is formatted for asMSX.

BitBuster_v12_VRAM_depacker_(16Kb)
Pletter_v05b_VRAM_depacker_(16Kb)

I will have to find time in the coming weeks to work on new releases working with 128Kb VRAM.

By dvik

Prophet (2176)

dvik's picture

19-02-2008, 20:30

Very Nice! I took a quick look at the code and I saw that the OUTs are sometimes too close and will probably casue VRAM corruption on MSX1. Its not hard to fix, just add a few nops in some cases. The closest two consecutive OUTs can be is 28 Z80 cycles.

By Metalion

Paladin (909)

Metalion's picture

19-02-2008, 20:36

You are right, dvik, I thought of that while writing the code then forgot all about it ... Eek!Eek!
It will be included in the next release.

By Metalion

Paladin (909)

Metalion's picture

20-02-2008, 09:00

The closest two consecutive OUTs can be is 28 Z80 cycles.
dvik, when you say 28 Z80 cycles, what do you mean ?
M-cycles or T-states ?

I went back to MSX Assembly Pages for reference, and it says that 7 T-states are needed between two OUT instructions.

By jltursan

Prophet (2076)

jltursan's picture

20-02-2008, 10:34

He's talking about T-states, it's a limitation imposed by the VDP itself and the full info can be found in the 9918 datasheet page 2-4. In screen 2 there's a full access window every 8 microseconds (maximum); so being 3,54Mhz the Z80 speed, 28 T-states are needed to fully secure the data transfer if you want to send the data out of the VBlank. That's why about two NOPs are needed using an OUTI (18+5+5).

By Metalion

Paladin (909)

Metalion's picture

20-02-2008, 12:01

Actually, Z80 frequency is 3.579545 MHz so the math comes to 28.63, roughly 29 T-states.
You must include the OUT instruction, so it means we need 18 additional T-states before the next VRAM access. That's a lot of unused CPU time, but if it is needed, so be it.

But what about MSX2 and above ?
What can we conclude from the V9938 datasheet (pages 121 to 125) ?
It says page 123 that the typical VRAM read/write cycle time is 279 ns, which translates into 1 T-state. Is that correct ?

By jltursan

Prophet (2076)

jltursan's picture

20-02-2008, 12:48

Yes, the OUT instruction must be included; so you need to fill the gap with NOP's (or any other useful operation that can be placed here Wink). In practice it's only to increase the compatibility to the 100% of MSX models; but usually 1 NOP is enough Tongue
AFAIK the MSX2 VDP doesn't need delay between data transfers; but in TR machines I think there's something about that, not sure...

By sjoerd

Hero (593)

sjoerd's picture

20-02-2008, 13:41

The delay of 2 nops is also needed on MSX2. On TurboR machines there is no need for nops in R800 mode.

By ARTRAG

Enlighted (5824)

ARTRAG's picture

20-02-2008, 13:52

The delay of 2 nops is also needed on MSX2. On TurboR machines there is no need for nops in R800 mode.
Why msx2 needs 2 nops?

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