Extra WAIT signal on all instructions ?

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By Metalion

Paragon (1622)

Metalion's picture

26-01-2014, 09:53

Hi everyone,

Reading the Z80 documentation, I'm wondering if the extra WAIT signal is used on every instruction. There's a first WAIT signal poll from the CPU on fetching the instruction from memory, but that seems to be included in the M1 cycle.

Apart from that, it seems to me that the extra WAIT signal is only needed if the instruction accesses the memory.

That's important to know. Let's see those 2 examples :

ld      a,(memory)
exx
ld      a,b
exx

If an extra WAIT signal is needed on all operations, than the second code is slower than the first : (4+1+4+1+4+1)=15 clock cycles versus (13+1)=14. If not, than the first code is slower : (13+1)=14 versus (4+4+4)=12.

What do you think ?

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By hap

Paragon (2042)

hap's picture

26-01-2014, 10:34

Yes, the 2nd one is slower.

M1 cycle is the opcode fetch cycle. It does not matter if the instruction has an extra memory read/write. So, on MSX, *every* opcode includes a wait cycle per each M1 cycle.

Bare Z80:
T1, T2, T3, ..

MSX:
T1, T(wait), T2, T3, ..

*edit* Keep in mind that instructions with a prefix have two M1 cycles; means two extra wait cycles inserted on MSX.

By anonymous

incognito ergo sum (116)

anonymous's picture

26-01-2014, 10:43

The WAIT signal is already included in the M1 cycle, in T2, on a bare Z80.

Do you mean that the WAIT signal on the MSX lasts for 2 clock cycles instead of 1 ?

bare Z80 M1 : T1, T2 (WAIT), T3, T4
MSX Z80 M1  : T1, T2 (WAIT), T2' (WAIT), T3, T4

Is that it ?

By msd

Paragon (1510)

msd's picture

26-01-2014, 11:08

No just one wait state added.

By hit9918

Prophet (2927)

hit9918's picture

26-01-2014, 11:44

@Metalion,
" it seems to me that the extra WAIT signal is only needed if the instruction accesses the memory."

every instruction acesses memory - the opcode.
And ONLY opcodes gets an extra wait cycle. That's why it is called "M1", the first machine cycle.

And on a double byte opcode, you got to add two times the wait cycle.
Immedeates and addresses and relative addressing bytes and port numbers dont count as M1, dont get an extra wait.

"The WAIT signal is already included in the M1 cycle, in T2, on a bare Z80."
Nooo.

The emulators got this. You could compare rasterbeams to see which one is faster.

The background is that in the 4 cycles of opcode, the z80 does memory refresh.
Therefore there is actualy more action than in the ordinary 3 cycles memory load.
Need a wait when it is too fast for the board. On MSX that is the case.

By Metalion

Paragon (1622)

Metalion's picture

26-01-2014, 11:44

So it's rather :

bare Z80 M1 : T1, T3, T4
MSX Z80 M1  : T1, T2 (WAIT), T3, T4

Is it ?

By hit9918

Prophet (2927)

hit9918's picture

26-01-2014, 12:03

Why on the bare z80 you leave out T2?
bare z80 takes 4 cycles, MSX 5 cycles.

By hap

Paragon (2042)

hap's picture

26-01-2014, 12:05

Nono Tongue nevermind that M1 and T-states stuff if you don't understand it.

Just remember this: on MSX, 1 extra cycle per instruction, plus one more cycle on instructions with prefix (CB, ED, DD*, FD*)

By Metalion

Paragon (1622)

Metalion's picture

26-01-2014, 12:12

Well, hap, I would have like to understand, that's the point of my question, you see ... Hannibal
But OK, I'll stick to the facts, and nothing but the facts, mam' ... Cool

By hap

Paragon (2042)

hap's picture

26-01-2014, 12:25

See, you were asking something very specific, but without understanding the basics underneath it.

By hit9918

Prophet (2927)

hit9918's picture

26-01-2014, 12:34

@Metalion, now I notice your notation "T2 (WAIT)", like T2 is the WAIT.
No, it is like "insert it into diagram", maybe like this:

1 wait 2 3 4

Actualy, I think any amount of waits could be inserted.
e.g. on the CPC, due to video DMA the cycle table gets stretched out to multiple of 4 cycles.

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