you can also removed the circuit.. msx will still work without m1.. only some vdp outs become to fast
See, you were asking something very specific, but without understanding the basics underneath it.
Basically, I don't think I like your answer, hap. I'm trying to learn and to understand things, and all you say is : "forget about it, you're too dumb for that". I've read the Z80 documentation, and I think I pretty well understand timing and cycling of the CPU, thank you.
@Metalion, now I notice your notation "T2 (WAIT)", like T2 is the WAIT.
No, it is like "insert it into diagram", maybe like this:
1 wait 2 3 4
Well, if you read the Z80 documentation, you'll see that T2 includes the WAIT signal polling. But OK, I get the picture. Actually, the polling starts in T2, but since the clearance of the WAIT signal is longer than usual, an extra cycle is inserted after T2.
During T2 and every subsequent Tw, the CPU samples the WAIT line with the falling edge of Clock. If the WAIT line is active at this time, another WAIT state is entered during the following cycle. Using this technique, the read can be lengthened to match the access time of any type of memory device.
Thanks.
Basically, I don't think I like your answer, hap. I'm trying to learn and to understand things, and all you say is : "forget about it, you're too dumb for that". I've read the Z80 documentation, and I think I pretty well understand timing and cycling of the CPU, thank you.
Wow, that's exactly what I said? o_O
No, I didn't mean to insult you at all.
welcome to MRC, hap
^ That wasn't necessary.
Wow, that's exactly what I said? o_O
No, I didn't mean to insult you at all.
OK, let's agree that it was a misunderstanding, then.
Sorry for my reaction.
