Msx1 race engine

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By thegeps

Hero (541)

thegeps's picture

11-08-2020, 13:51

My scrolling engine works by constantly redefine first 30 tiles og each block (upper,middle and bottom). So to scroll every pixel it writes 30x8x3=720 bytes on pattern table and 30x8x3=720 bytes on color table. Then 768 bytes to write the whole nametable.so 1440+768=2208 bytes (I use double buffering in an unusual way, every frame I redefine tiles from 0 to 29 and every odd frame tiles from 128 to 157 so every odd frame I write on nametable tiles from 0to29 and every frames tiles from 128 to 157)
Mirroring color table I'll have to write 480 bytes less per frame. Don't know if worthy (but we are OT here, if you have suggestion write me on Freedom Fighter WIP thread)

By smx

Resident (40)

smx's picture

11-08-2020, 17:34

Thank you all for the comments: I have yet to read them thoroughly and try to add the various contributions to this engine.

However, I wanted to give an explanation on what was done: the idea comes from PitStop 2 on C64 but after several attempts I am came to the conclusion that it is not possible to do this for Msx 1.

I come to the point, the fundamental element for a race game is the alternation of white\red and white\gray stripes.
The more alternations we manage to do, the more we will have the impression of running fast.
To do this I thought it was necessary to alternate the colors through registers in order to have a very fast effect.
But here comes the problem, there are so many tiles and having to update pattern table, color table and name table it is too expensive.

So I decided to use tiles in an unusual way (at least for me), ie the color table is loaded only once at the beginning and is valid for all 11 screens you see in the video.
In this way to have the effect of the speed it is enough to alternate the value of the registers (5 steps).
The patterns on the other hand are dynamically loaded into VRAM and determine the shape of the circuit, but this is not a
big problem as the speed with which you change the shape of the circuit is not so important.

Another problem was the high number of tiles, to do this I used the first 2 banks in VRAM and I show 3 lines for bank 0 and 4 lines for bank 1 (I used almost all available tiles).

I didn't use any double buffer, also because I don't know where to go to place all the patterns (too much tiles).

Test03

At the moment the engine is partly in basic and partly in assembler, just to facilitate testing.
As soon as possible I will convert everything to assembler and I believe that the result will certainly be better

By ARTRAG

Enlighted (6429)

ARTRAG's picture

11-08-2020, 17:56

Very nice! Should you need two pages in screen 2 with the above constrains (non working on Thisiba video chips) this is a possible vram layout

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; defb 0x02 ; Reg# 0 000000[M3][EV]
; defb 0x62 ; Reg# 1 [4/16k][BLANK][IE][M1][M2]0[SIZE][MAG]
; defb 0x06 ; Reg# 2 0000[NAME TABLE BASE ADDRESS] = 1800h

; defb 0x9F ; Reg# 3 [COLOR BASE ADDRESS] = 2000h ; hybrid mode for colors
; defb 0xFF ; Reg# 3 [COLOR BASE ADDRESS] = 2000h ; regular mode for colors

; defb 0x1F ; Reg# 3 [COLOR BASE ADDRESS] = 0000h ; hybrid mode for colors
; defb 0x7F ; Reg# 3 [COLOR BASE ADDRESS] = 0000h ; regular mode for colors

; defb 0x00 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS] = 0000h ; hybrid mode for patterns
; defb 0x03 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS] = 0000h ; regular mode for patterns

; defb 0x04 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS] = 2000h ; hybrid mode for patterns
; defb 0x07 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS] = 2000h ; regular mode for patterns

; defb 0x36 ; Reg# 5 0[SPRITE ATTRIBUTE TABLE BASE ADDRESS] = 1b00h
; defb 0x07 ; Reg# 6 00000[SPRITE PTRN GNRTR BASE ADDRESS] = 3800h
; defb 0x01 ; Reg# 7 [TEXT COLOR 4bts][BACKDROP COLOR 4bts]

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
disp_page1: ; page 1 active
setVdp 3,0x9F ; colours at 0x2000 (hybrid)
setVdp 4,0x03 ; patterns at 0x0000 (regular: used 0x0800 0x1000)
ret

disp_page0: ; page 0 active
setVdp 3,0x1F ; colours at 0x0000 (hybrid)
setVdp 4,0x07 ; patterns at 0x2000 (regular: used 0x2800 0x3000)
ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; write page 1
write_page_1:
ld hl,0x2000
ld (pctbase),hl ; write colours at 2000h
ld hl,0x0800
ld (pgtbase),hl ; write pattern at 0800h & 1000h
call tileupdate

ld hl,(curframe)
ld bc,6
add hl,bc
ld (curframe),hl
ret

; write page 0
write_page_0:
ld hl,0x0000
ld (pctbase),hl ; write colours at 0000h
ld hl,0x2800
ld (pgtbase),hl ; write pattern at 2800h & 3000h
call tileupdate

ld hl,(curframe)
ld bc,6
add hl,bc
ld (curframe),hl
ret

By albs_br

Expert (117)

albs_br's picture

01-09-2020, 20:29

What if you use two name tables, alternating between them?
One at the usual address (6144), other at 7168 (1024 x 7), which is unused space of Screen 2 standard memory mapping.
Then we will have two version of each tile, one for each color.

	        start		end		size			
name table	6144		6911		768			the address can vary between 0 and 3C00h (15360), steps of 1024
color table	8192		14335		6144			color table can only be found at the address 0000h or 2000h (8192)
pattern table	0		6143		6144			it can only start at the address 0000h or 2000h (8192)
								
spr attr table	6912		7039		128			
spr patt table	14336		16383		2048			
								
free space	7040		8193		1154			
								
								
name table alternate	7168		7935		768			

Sorry if I'm repeating someone, didn't read the entire thread.

By albs_br

Expert (117)

albs_br's picture

07-09-2020, 21:04

I implemented this idea. Later I found that is the same original ideo of this post, but anyway.
Forum thread here

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