OUTI takes 1 extra cycle on Turbo machine

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By sd_snatcher

Prophet (2865)

sd_snatcher's picture

20-08-2018, 23:20

Grauw wrote:

To be clear, most MSX2+ machines also have these wait cycles, even two of them:

0 cycles: Sony HB-F1XDJ, Sony HB-F1XV
1 cycle: Panasonic FS-A1WSX, Panasonic FS-A1ST, Panasonic FS-A1GT, Aucnet NIA-2001
2 cycles: Panasonic FS-A1FM (MSX2), Panasonic FS-A1FX, Panasonic FS-A1WX, Panasonic FS-A1WSX, Sanyo PHC-35J, Sanyo PHC-70FD, Sanyo PHC-70FD2, Al Alamiah AX-370

Just some small corrections:

- The FS-A1WSX is listed twice. But it has the T9769C like the TRs.
- Some of the last batches of the FS-A1WX and PHC-70FD2 also were produced with the T9769C, so they also have 1 cyles

The Sanyo PHC-55FD2 is an MSX2 with the T9763 engine that is the predecessor of the T9769. I reckon that this also has the extra waitstate.

By sd_snatcher

Prophet (2865)

sd_snatcher's picture

20-08-2018, 23:34

It's a little known fact that the S1985 also has the extra 1 waitstate generator for the VDP. It is described on the page-9 of its application manual. But it can be (and usually is) disabled by a hardware jumper.

It seems that this was implemented to allow this engine to also be used with the MSX1 VDP.

But the S1985 VDP waitstate generator is bugged:

- When enabled, it will generate bogus /CSW and /CSR signals that cause VRAM access corruption even at 3.58MHz
- When disabled, it will generate bogus /CSW and /CSW signals that cause VRAM access corruption at speeds higher than 4MHz even if the V9958 /WAIT function is enabled

By NYYRIKKI

Enlighted (5026)

NYYRIKKI's picture

21-08-2018, 00:46

Eugeny_Brychkov wrote:

however it seems register #6 has bit 7 which causes machine to reboot. This bit seems not to be documented.

You definitely got my full attention... I don't remember finding this kind of thing while testing (but it was already many years ago, I might have forgot something)... I bet the reboot is not the intended function, but a side effect of something else... Would be nice to know why this happens.

By Eugeny_Brychkov

Paragon (1032)

Eugeny_Brychkov's picture

21-08-2018, 08:27

sd_snatcher wrote:

But the S1985 VDP waitstate generator is bugged:

OMG... Sad

NYYRIKKI wrote:

I bet the reboot is not the intended function, but a side effect of something else...

Reboot is the response action we witnessed when trying to write differing value to this bit. I suspect it also must be related to CPU operation condition as this bit is too close to Z80/R800 and ROM/DRAM bits.

By WORP3

Paladin (803)

WORP3's picture

23-08-2018, 12:05

Why is an OUTI not 16 cycles instead of the 18 you are referring to? Where are the two additional t-states coming from?
You where saying that the two addition ones are for opcode fetching. Does this mean that for each opcode, the number of t-states inside the Zilog datasheet are to low and additional t-sates for fetching should be added?

By Grauw

Enlighted (7453)

Grauw's picture

23-08-2018, 14:01

@WORP3 Due to the M1 wait. As I wrote on the previous page:

Grauw wrote:

On MSX ex (sp),hl takes 20 cycles, and ld a,(ix + 0) takes 21. This is due to the M1 wait cycle which is present on the MSX architecture (and btw also documented in the Z80 manual), and due to the latter having two M1 cycles because it’s a prefixed instruction.

See this instruction reference table, particularly the “Timing Z80+M1” column, which is the one you should use as instruction timing reference for MSX.

Since OUTI is a prefixed instruction it has two M1 cycles, one for the ED prefix and one for the opcode that follows it. And thus two extra wait states are added.

By WORP3

Paladin (803)

WORP3's picture

30-08-2018, 11:52

Grauw wrote:

@WORP3 Due to the M1 wait. As I wrote on the previous page:

Grauw wrote:

On MSX ex (sp),hl takes 20 cycles, and ld a,(ix + 0) takes 21. This is due to the M1 wait cycle which is present on the MSX architecture (and btw also documented in the Z80 manual), and due to the latter having two M1 cycles because it’s a prefixed instruction.

See this instruction reference table, particularly the “Timing Z80+M1” column, which is the one you should use as instruction timing reference for MSX.

Since OUTI is a prefixed instruction it has two M1 cycles, one for the ED prefix and one for the opcode that follows it. And thus two extra wait states are added.

Thanks for your reply. No wonder that the MSX system isn't doing real wonders on the VDP :( The z80 was already slow, this makes it even worse. Ok, what's done is done apparently.

By sd_snatcher

Prophet (2865)

sd_snatcher's picture

30-08-2018, 15:08

That's why I love turbos! Smile

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