Respecting the 29 T-states timing

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By hit9918

Prophet (2905)

hit9918's picture

23-01-2014, 15:39

@Metalion,
yes, MSX1 in blank lines you can do fast unrolled OUTI.
According to 9918 docs it even can take plain OUT easily.
Because in blank lines, there are no vram fetches for display.

Wait for vblank, change border color, copy, change border color back.
Then you can see whether your code is about to hit display area.
See the difference between 60hz and 50hz machine.

One actualy could set the display to blank mode while doing fast acess.
Like when the game has jitter and sometimes hits display.
The top of display would sometimes disapear flicker.
Better than getting corrupt vram writes.

By Metalion

Paragon (1451)

Metalion's picture

23-01-2014, 15:41

Thank a lot, hit9918, I will try this method tonight.
Wink

By ARTRAG

Enlighted (6564)

ARTRAG's picture

25-05-2014, 22:36

Sorry to resurrect this topic, would his code work on any msx1 ?
Bluemsx seems to report a problem after the out (0x98),a), but I cannot see why...

1:	outi	
	nop
	nop
	out (0x98),a
	nop
	nop
	jr	nz,1b

By hit9918

Prophet (2905)

hit9918's picture

26-05-2014, 01:17

better is

loop:	outi
	nop
	nop
	nop
	out (c),a
	jp nz,loop

one got to imagine the action on the bus happens in last cycle of the out.
the difference is in the headers of the various out instructions.
then the delay is the out instruction plus the instructions ahead of it.

time between outi and out is

5	nop
5	nop
5	nop
14	out (c),a	;using out(c) to get 14 instead 12 cycles
--
29


time between out and outi
11	jp nz,loop	;jp takes 11, a jr that is taken takes some more.
18	outi
--
29

mhm two times 29, that went nice Smile

By Grauw

Ascended (10135)

Grauw's picture

26-05-2014, 01:54

hit9918 wrote:

one got to imagine the action on the bus happens in last cycle of the out.

If I understand the Z80 user manual correctly, the bus I/O takes place in the last three cycles.

I was wondering about this in the context of OPL wait requirements, whether I should count from the start / end of the first OUT to the start / end of the next OUT, or whether I should count from the end of the first OUT to the end of the next OUT minus 3 (start of the bus request)…

For example, the OPLL wait requirement after an address write is 3.4 µs, or 12 Z80 cycles at 3.58 MHz. At 3.58 Mhz, can I output addresses to it with OUT (n),A instructions back-to-back (12 cycles), or do I need to introduce 3 wait cycles between them? I suspect the latter…

By TheSpecialist

Expert (113)

TheSpecialist's picture

26-05-2014, 02:08

wouter_ wrote:
Grauw wrote:

What is the minimum wait for the v9938?

on V9938 OTIR or a sequence of OUTI instructions is fine.

Note that a sequence of OUTI is not fine for SCREEN0 WIDTH80. There you will need OUTI + NOP (or OTIR).

By Grauw

Ascended (10135)

Grauw's picture

26-05-2014, 03:20

So I was thinking, where is this 29 cycles wait information coming from?

Looks like section 2.1.5 of the TMS9918A application manual has a pretty clear description of the VRAM write timing requirements…

It seems noteworthy that the 8 µs (29 cycles) wait time only applies to Graphics I and II modes with sprites enabled. In Text I mode it’s 3.125 µs (12 cycles), and in Multicolor mode it’s 3.5 µs (13 cycles). Also during blanking it’s just 2 µs (8 cycles).

As for the V9938, the application manual section 1.4 directs us to the V9938 datasheet for the timing requirements; this datasheet can be found as “part 2” at the bottom of the scanned version of the V9938 application manual in the CPU-MSX-Video and the MSX-VIDEO-VRAM sections. You can also find these in the V9958 application manual, it seems to be identical.

I see lots of squiggly lines and numbers there so it seems the information is there (also register access timing), but it’s too late at night for me right now to make sense of it :).

By hit9918

Prophet (2905)

hit9918's picture

26-05-2014, 02:58

@grauw,
memory acess is 3 cycles, port is 4 cycles.
port acess has 1 automaticaly inserted waitstate.

the details of bus diagram, the only thing I know that one can ignore it in the 9918 business,
because the manual gives an imprecise spec and the chip suceeded a bit faster tests.

I think normaly bus latencies should not affect how frequent the internal gear can change, i.e. just count cycles and not bother with the bus diagram.
and I think in practice the docs one got just aren't precise enough for such details.

when the OPL spec is near 12 cycles, I would use the 14 cycles out (c).
I wonder why it has a speed limit, is it about sample RAM?

By Grauw

Ascended (10135)

Grauw's picture

26-05-2014, 03:10

hit9918 wrote:

memory acess is 3 cycles, port is 4 cycles.
port acess has 1 automaticaly inserted waitstate.

This wait was included in the 3 cycles I mentioned. Look at the Timing / Input or Output Cycles section of the Z80 CPU User Manual. IORQ and RD / WR don’t go low yet in the first cycle.

I agree with the rest you wrote :).

hit9918 wrote:

I wonder why it has a speed limit, is it about sample RAM?

No, OPLL doesn’t have sample RAM. This is just the wait required to write the address of the internal register before writing data. Data writes take even longer to process (23.5 µs).

By hit9918

Prophet (2905)

hit9918's picture

26-05-2014, 03:13

Max speed of registers, funny.
On the VDP it's not the registers, it's the vram acess slots.
And yes, in blank lines it can take all the z80 can give.

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