RST 30h

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By Eugeny_Brychkov

Paladin (1017)

Eugeny_Brychkov's picture

10-10-2018, 16:07

Grauw wrote:

And since the testing surface of possible configuration alone is so large, it’s pretty difficult to test it properly.

I would not fully agree to it. Slot subsystem is not so complex if you know how it works, and there's very defined flow of operation how to change it. But I fully agree on shortcuts, however I am sure the whole slot switching code will not be big or complex if implemented properly.

Grauw wrote:

Not sure if those routines can "just be copied from the main ROM"

They must be fairly good as the only failure is their location under specific circumstances Smile

Grauw wrote:

So I could explain all this, but my short recommendation is always: "don’t do it unless you must".

Fully agree with this. Within the ARTRAG's original quesiton I would first think if I can change software specifications not using bank 0 at all. But as my research shows, bank 0 RAM will be only accessible for RDSLT and WRSLT (as they execute from main ROM CPU bank 1), thus can be used to store slow data.

By Grauw

Enlighted (7410)

Grauw's picture

10-10-2018, 19:43

Eugeny_Brychkov wrote:
Grauw wrote:

And since the testing surface of possible configuration alone is so large, it’s pretty difficult to test it properly.

I would not fully agree to it. Slot subsystem is not so complex if you know how it works, and there's very defined flow of operation how to change it.

To know how it works conceptually is one thing. To reliably be able to make it work in all cases is another, what with swapping out the top of the TPA including stack, needing support code in multiple pages, calculating the correct values, updating all the BIOS tables in system memory, special casing expanded slots vs. non-expanded slots, etc. Just a lot of steps + many testing scenarios.

Grauw wrote:

But as my research shows, bank 0 RAM will be only accessible for RDSLT and WRSLT (as they execute from main ROM CPU bank 1), thus can be used to store slow data.

That’s a good find! I already started thinking after I wrote it that huh, why does it work for RDSLT and WRSLT actually. Indeed it looks like they made a special code path for reading from slot 0 page 0.

So given that they did take this case into account explicitly for RDSLT and WRSLT but not for CALSLT and CALLF pretty much implies that they do not support it on purpose (otherwise it would make a very odd omission), thus you are not supposed to interslot call code in page 0 in the BIOS environment. One reason might be because the ISR lives there.

By zeilemaker54

Master (220)

zeilemaker54's picture

10-10-2018, 22:32

Actually, there is one exception for the calslt/callf from mainrom to page 0 rule, that is a call to the subrom bios (which is on page 0). This is supported (by a neat trick with the crusial part of the calslt/callf code exactly the same and at the same addresses).

By DarkSchneider

Paladin (754)

DarkSchneider's picture

11-10-2018, 09:17

Agree with I like to work for an OS for that reason. A more tested environment with extra functionality.

I think copy the functions is not safe (even if it seems to work) because they can have jumps, that would crash.

Yes the subslot system is not hard to understand, but it can be a hell to work with. The subslot selection should have been placed in a hardware piece accessed by a port, instead on the own RAM!

The reason about these "faulty" systems could be any, from they ignoring some specification, to a not full specification lacking some advices about hardware design.
In any case, I wonder why, having an already working set (all the existing systems with RAM at slot 3), they changed it to slot 0, why they needed the slot 3 free?

The problem here is mainly for BASIC software that want to use all the RAM, i.e. putting routines in page 0. Also, I wonder how disk software for 64KB not using DOS (I think many didn't use DOS as base) like Falcom or Microcabin games work as they have to put RAM in page 0 after boot.

By gdx

Prophet (2270)

gdx's picture

11-10-2018, 15:39

"Eugeny_Brychkov" wrote:

So let's return to one of my previous questions - what are the machines having RAM in slots 0-1, 0-2 or 0-3 in CPU bank 0?

MSX2:
Daewoo CPC-300/300E/300K
Daewoo CPC-400/400S
Pioneer UC-V102
Sony HB-F5 (and probably HB-T7)
Sony HB-F500P/D/F
Talent DPC-300
Victor HC-80/90/95

Zemmix:
Daewoo CPC-61
Daewoo CPG-120

Hidden MSX2:
Pioneer UC-V102

(non-exhaustive list)

"DarkSchneider" wrote:

They are what I call "faulty systems", because IMO they are not complying with the specification.

What makes you say that?

By Eugeny_Brychkov

Paladin (1017)

Eugeny_Brychkov's picture

11-10-2018, 15:50

I think the rationale of putting RAM into CPU bank 0 in slot 0 is extremely simple: saving on glue logic and thus cost of the materials. Do all these machines have MSX-engine built on discrete logic?

By mars2000you

Enlighted (5372)

mars2000you's picture

11-10-2018, 15:52

gdx wrote:

Sony HB-F5 (and probably HB-T7)

No, HB-T7 has the same slot structure as HB-T600, RAM is in slot 3-3.

By ARTRAG

Enlighted (6015)

ARTRAG's picture

11-10-2018, 21:33

It would be a good idea to record the findings in wiki and online docs about the bios

By DarkSchneider

Paladin (754)

DarkSchneider's picture

12-10-2018, 08:55

gdx wrote:
"DarkSchneider" wrote:

They are what I call "faulty systems", because IMO they are not complying with the specification.

What makes you say that?

That some functions does not work like expected, like ENASLT or CALLF.

By Grauw

Enlighted (7410)

Grauw's picture

12-10-2018, 09:16

Is the fact that WRSLT and RDSLT have explicit handling for the slot 0 page 0 case and CALSLT, CALLF and ENASLT do not, not sufficient evidence that it is intentionally not supported?

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