Screen 4 VRAM Question | MSX Resource Center (Page 2/2)

Paragon (1622)

24-08-2022, 19:52

After doing some research, I found that the 4th bank has been confirmed by wolf_, sjoerd and PingPong here : https://www.msx.org/forum/development/msx-development/tiles-...

So my question remains:

Metalion wrote:

As everybody knows, in screen 2 there are restrictions on the value of register R#3 (color table address) and R#4 (pattern table address). R#3 can only be 7Fh or FFh (address 0000h or 2000h), R#4 can only be 03h or 07h (address 0000h or 2000h).

Are those restrictions still there for screen 4 ?

By Micha

Expert (98)

24-08-2022, 20:31

Metalion wrote:

As everybody knows, in screen 2 there are restrictions on the value of register R#3 (color table address) and R#4 (pattern table address). R#3 can only be 7Fh or FFh (address 0000h or 2000h), R#4 can only be 03h or 07h (address 0000h or 2000h).

Are those restrictions still there for screen 4 ?

If I understand the Konamiman Github page (here correctly then for the Pattern Table there are the same restrictions in Screen 4 as in Screen 2, but for the Colour Table you can use 3 extra bits from register R#10 in screen 4.

By ARTRAG

Enlighted (6933)

03-09-2022, 16:14

Basically you can zero some of the bits in R3 and R4 and get as result that the 3 tile banks on the screen appear at the same address (you can also have two banks equal and a 3rd independent).
If you look for hybrid modes in screen 2 on the forum you will find more details on how the lower bits in those registers mask the vram pointer used by the vdp to render the colors and the patterns on the screen.
The main difference is that the sprites in the v9938 are not affected by these bits, while the tms9918 shows glitches on sprites 8 and upper when the pattern table is 'rolled' on one single bank (the upper sprites appear replicated multiple times).

By ARTRAG

Enlighted (6933)

03-09-2022, 16:18

Look here
https://www.msx.org/forum/development/msx-development/undocu...