TMS VDP timing testing

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By hit9918

Prophet (2787)

hit9918's picture

11-09-2018, 21:40

this subtle difference is because... it is MSX2 Big smile
but, when you say the longest gap is 21.33 cycles - but the 18 cycles outi works on MSX2.
you're maybe off by factor 2. the cycles in wouters diagram (the big pic) are 21Mhz cycles, 4 times the dotclock of 256 pixel mode.

meanwhile the MSX1 has a TI manual with problematic explanations

By TomH

Master (239)

TomH's picture

11-09-2018, 22:11

hit9918 wrote:

this subtle difference is because... it is MSX2 Big smile

Most of it is, but the timing diagram features the regular old TMS9918 at the bottom, showing refresh, text and character line costs, with 171 memory access windows occupying 342 cycles per line. You could very broadly describe it as eight blocks of 15-window VDP access with a single empty window between during pixels to collect all background and some sprite locations, plus the remainder of sprite locations and sprite graphics for the blessed four spread less-intensely throughout the border.

The diagram is here. Scroll to the bottom.

hit9918 wrote:

but, when you say the longest gap is 21.33 cycles - but the 18 cycles outi works on MSX2.
you're maybe off by factor 2. the cycles in wouters diagram (the big pic) are 21Mhz cycles, 4 times the dotclock of 256 pixel mode.

I didn't inspect the MSX2 section of the diagram.

By hit9918

Prophet (2787)

hit9918's picture

11-09-2018, 22:41

boy I forgot that this pic has MSX1 at the bottom Big smile

ok the slots are 16 boxes apart. 32 pixels, 21.33 cpu cycles.
I got no idea what makes it 27 cycles.

By Eugeny_Brychkov

Paragon (1035)

Eugeny_Brychkov's picture

12-09-2018, 20:59

I made a video playback engine basing on 27 T-cycles, seems to work well!

By TomH

Master (239)

TomH's picture

21-09-2018, 16:25

hit9918 wrote:

ok the slots are 16 boxes apart. 32 pixels, 21.33 cpu cycles.
I got no idea what makes it 27 cycles.

As it turns out, the answer in the data sheet: it confirms a maximum 16 windows separation, but almost mentions a 2us setup time for making a transfer.

So I think the issue is:

  • if your attempt to initiate a transfer overlaps an available access window, the VDP won't use that window;
  • since you are not running exactly in phase with the available windows, you therefore need each write to be spaced so that there is enough time for (i) 2us; plus (ii) enough time to get from the end of the 2us to the end of the next access window.

So not 16 windows, but 2us + 16 windows.

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