Uncovering the R800

Conveyor check R800.

Is it possible to make a register-register command with the R800? Then. Jump 0x1000. And again make the command register-register.

How many CPU tacts spent?

No. The R800 has 4 RAS pins: RAS0 to RAS3. This means that the R800 supports up to 4 banks, each with DRAM chips as big as 4M.

The R800 seems to support DRAMs with 256k, 1M and 4M capacities. In the ST there is 1 populated bank with 256k. The GT has 2 banks with 256k each. On both PCBs only 2 banks are connected, RAS2 & RAS3. Pins RAS0 & RAS1 a left unconnected.

The questions that comes to mind is, in case the R800 is populated with more memory, how much would actually be visible to the Z80? There are many posts about Turbo-Rs with 1M. So this seems to work fine. There is a couple comments about 4M somewhere in the internet but there is some questioning if that configuration really worked properly. Looking at a post about a while back, reviewing the modifications, I got the impression that the modification would fail to refresh the upper 3/4s of the DRAM chips used. So this may be the cause of the issue. But I do not know for sure.

Interesting Edevaldo!

I think these signals would not be separated without reason (like the VDP has CAS0 and CAS1 allow it to access memory faster for screen 7/8), what do you think is the reason they separated those four RAS signals like that?

At the time the R800 was designed I do not think 16Mx4 chips (or even 16Mx1) existed (need to confirm). Those DRAM sizes, pinouts and operation were/are standardized by JEDEC, they make roadmaps. So when you are designing a chip you know the kind of memory will exist 3-4 years ahead. By the time the R800 was designed maybe even the 4M by "x" chips existed only on paper or were super expensive, being used in high end works-station class hardware. Even most PCs/Macs at the were shipped with less than 1/2MB of RAM and were shipped with 8-16 ram chips to reach those amounts. 1Mx1 and 256kx4 chips were getting common.

For those reasons I believe the 4 banks are there only for "future" capacity. For speed purposes you normally use CAS.

It was a common technique at the time to interleave memory banks to achieve faster transfer speeds (like the VDP does). This would normally be done by having each bank being driven with its own #CAS signal. Fast page mode DRAMs read the entire row(64-4096 bytes depending on chip size) when you lower the #RAS signal, then you can read any of those bytes quickly with the #CAS signal. So it may take (just a typical example) 60ns to read a ROW, but then you can read any byte in that row in about 40ns. And if you interleave the banks, you can read a byte every ~20ns by driving their #CAS signals in oposition. If you didn't use this fast page mode and interleaving you would be limited to 110ns cycle time in a fast 60ns DRAM chip.

On the PC/Mac worlds this started to be used on very high end 386s and 68030s, VGA hardware. Then it became more common until SDRAM started to be used. But the technique was probably already used in mainframes by early 70s. EDO DRAM simplifies the interleaving implementation and allow even faster bursts, so all computers that used EDO were capable of interleaving.

The R800 may have the DRAM operation embedded in its design. It is known that it takes an extra cycle when there is need for a page change and DRAM refresh stops the cpu to perform a "batch" of refreshes.

I'm not sure if this behavior can be disabled... If it could, there is some performance to be gained by using SRAM. But I'm not sure this gain would be more than a handful of %.