Uncovering the R800

Supporter (1)

15-11-2019, 05:10

I've got a copy of R800 Users manual.
https://1drv.ms/u/s!Ak1g1LqBUnx_6V3r9UO53wkXqL-b?e=h4egjz
It was published in japanese magazine "DATUM" Octover, 1990 from CQ Publishing Co.,Ltd.

By lintweaker

Champion (474)

15-11-2019, 09:39

juangotoh wrote:

I've got a copy of R800 Users manual.
https://1drv.ms/u/s!Ak1g1LqBUnx_6V3r9UO53wkXqL-b?e=h4egjz
It was published in japanese magazine "DATUM" Octover, 1990 from CQ Publishing Co.,Ltd.

Excellent find! Thanks!

By Grauw

Ascended (10821)

15-11-2019, 10:09

Great!

By Piter Punk

Master (232)

15-11-2019, 21:07

juangotoh wrote:

I've got a copy of R800 Users manual.
https://1drv.ms/u/s!Ak1g1LqBUnx_6V3r9UO53wkXqL-b?e=h4egjz
It was published in japanese magazine "DATUM" Octover, 1990 from CQ Publishing Co.,Ltd.

Wow! It's a great thing to have his information available!

Very nice find and great attitude making it available to the MSX community!

By Manuel

Ascended (19678)

16-11-2019, 00:01

Now we need someone who can read Japanese to translate it or to check whether it contains new information

By Edevaldo

Master (156)

16-11-2019, 04:58

I do not know Japanese but it has plenty of useful information... google image translations helps (at least when it is not hilarious).

It describes better the new interrupts and gives the addresses they would vector to if enabled (page 154).
The DMAs are not limited by 64k boundaries...

Page 158 details the memory mapping (mapper). It seems the 64k memory address is divided in 8 pages and those can physically map to 16MBytes. Interrupts seems to force the first page to be page zero.

It also describes a little how the rest of the system accesses the DRAM. And the same page describers the effects of the pin FTREN being high. Which is interesting.

Page 163 gives some detail on the internal registers. There are two "registers", an address register (CSREG=0, A0=0) and a data register (CSREG=0,A0=1). The first point to one of 128 internal registers, that are described in English in the next pages. The first many register form the memory mapping mechanism. Very straightforward.

Next are the DMA registers. Seem clear as well, 24 bit addresses for source and destination, 16 bit for count and an 8 bit control register.

Finally interrupt vector (a little obscure) and the interrupt masks.
Starting on page 173 it describes a little of the pipeline (instructions fetch is do in parallel with previous instruction execution) and describe the impact of DRAM access in instruction cycles. Like when it goes over a 256byte page boundary or hits a memory refresh.

I need to check the instruction tables in more detail to check if there is any instruction or addressing mode that is different from what the Z80 offered.

There is enough information there to hack a turbo-R to enable the 24-bit memory address, allow use of the DMAs and extra interrupts.

I was surprised that the R800 had 8kbyte pages, breaking with the 16k tradition of the MSX. But it shows that they may had compilers in mind when designing the R800. With 8 pages it is a lot easier to write a compiler that manages code segments in multiple pages and copy of data between pages becomes a lot simpler, for example.

But it does not seem there is any 16-bit processor hidden there.

This document is a great finding!

By ARTRAG

Enlighted (6977)

16-11-2019, 12:12

Great Finding.... It should be translated and published in English.
After 30 years finally we could understand what the r800 does

By NYYRIKKI

Enlighted (6092)

16-11-2019, 13:28

juangotoh wrote:

I've got a copy of R800 Users manual.
https://1drv.ms/u/s!Ak1g1LqBUnx_6V3r9UO53wkXqL-b?e=h4egjz
It was published in japanese magazine "DATUM" Octover, 1990 from CQ Publishing Co.,Ltd.

This must be the best "my first post here" ever. :)
Great find, thank you for sharing and welcome!

By Edevaldo

Master (156)

16-11-2019, 19:08

Reading the document I wonder why they didn't design the Turbo-R in a way to use the new features. For the memory mapping and DMAs to be useful they only needed to select two IO addresses to access those R800 registers.

I wonder if there is some hardware bug or if the 16MB addressing mechanism would conflict with the rest of the machine somehow. Like a feature missing in the chipset to be really able to use it.

What is not entirely clear to me also, is how the MSX memory space (ROM, SLOTS...) are mapped into R800 16MB address space. It seems like the first 64K are the MSX adress range and that the DRAMs are mapped to start at 0x800000 & 0xC00000 respectively. But I need to spend more time deciphering the doc & diagrams.

If the R800 is accessing its own DRAM in this way (thought the first 64k as it does not uses the 24-bit addressing), it seems that any R800 access to the DRAM has to go from the R800 to the S1990 and back to the R800 and DRAM. And then data would have to make the reverse path. Weird. Need to read it more times to make sense of it.

By ricbit

Champion (438)

16-11-2019, 19:20

Whoa this is huge. Thanks for the scan!