an article about z80 affecting MSX computers was published

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By litwr

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11-09-2018, 15:02

@RetroTechie Thank you very much! I am a curious man and want to know more about MSX... BTW I have just published yet another part of my stories - https://litwr.livejournal.com/1575.html - it is about a "father" of MSX design. Wink

By TomH

Master (216)

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11-09-2018, 18:10

If I dare wade in:

  • the ZX Spectrum really really runs at 3.58Mhz, no waits, no pauses, when executing from ROM or from RAM that the video can't touch. Pauses take effect only when interacting with shared banks;
  • the primary effect of the contention mechanism on the CPC is to stretch data storage, instruction fetches are unaffected once in phase and therefore classic z80-style trying to keep things in registers is the smart thing;
  • the C64 doubles the video display resolution of the Vic-20 while using nearly the same clock rate for its RAM (actually it's marginally slower) through bad lines — ordinarily the CPU is halted for a shade more than a line for every eighth line of pixels. The mechanism used is the RDY line, which exposes another 6502 issue: its equivalent of WAIT can pause only read cycles. So to use it as a memory contention mechanism you have to assert it at least two cycles early, that being the maximum number of consecutive write cycles on a 6502;
  • the 8-bit Atari computers go one further and actually use a modified 6502 with an extra clock-stopping signal;
  • the Acorn Electron, close to my heart, is another interesting example of the monkeying necessary for a 6502 implementation. Programs in ROM run at a full 2Mhz. Access slows down to 1Mhz for RAM in the modes where the graphics screen is 40 bytes across. In 80-byte modes the CPU is also shut down entirely until the next border if it tries to access RAM while pixels are being serialised. Broad net effect: 2Mhz for ROM, 1Mhz for anything user-written in 160x256x2bpp or 320x256x1bpp, possibly as little as ~486Khz (!) for 160x256x4bpp, 320x256x2bpp or 640x256x1bpp.

I can think of nothing with a 6502 that matches the video bandwidth of a Spectrum, CPC or MSX that doesn't either pause the CPU periodically the processor to do so, or cost twice as much as the MSX/C64/Spectrum pack.

(EDIT: I liked the article though. You outwitted me twice: I progressed while mentally fuming over your failure to mention the Z80's much improved interrupt structure until you did. Then I wondered about failure to note the 4-bit ALU, until you did. I'll definitely make time to read the rest of the series.)

By litwr

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13-09-2018, 10:12

@TomH Thank you! I have also texts about 8080, 6502, ARM, VAX-11, 32016, ... but I need spare time to translate them.
6502 has 3 as the maximum number of consecutive write cycles - look at BRK instruction or the interrupt enter sequence. So we need at least 3 cycles. IMHO Commodore+4 uses the most interesting memory contention scheme.

By PingPong

Prophet (3123)

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13-09-2018, 13:41

litwr wrote:

@TomH Thank you! I have also texts about 8080, 6502, ARM, VAX-11, 32016, ... but I need spare time to translate them.
6502 has 3 as the maximum number of consecutive write cycles - look at BRK instruction or the interrupt enter sequence. So we need at least 3 cycles. IMHO Commodore+4 uses the most interesting memory contention scheme.

The C64's scheme is a classical scheme used on 6502 cpus of the era. Nothing special.
Basically it is a classical DMA implementation + the trick used to share 50% of the memory bandwidth without the need of bus arbitration. This is possible because of the peculiarities of the simple memory access scheme of the 6502, and the simplicity of the architecture (only one byte opcode, no need to extend memory cycles using two bytes opcode fetch, so no variable and no- predictable memory fetch duration)
Others processors required a more complex arbitration mechanics .

By TomH

Master (216)

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14-09-2018, 16:46

litwr wrote:

@TomH Thank you! I have also texts about 8080, 6502, ARM, VAX-11, 32016, ... but I need spare time to translate them.
6502 has 3 as the maximum number of consecutive write cycles - look at BRK instruction or the interrupt enter sequence. So we need at least 3 cycles. IMHO Commodore+4 uses the most interesting memory contention scheme.

Ugh, I was thinking of the various read-modify-writes, that write back the original value before writing the updated value. I had forgotten e.g. BRK that leads off (after operation and phoney operand fetch) with a push of both the PC and the flags register — for a three byte writes in a row.

PingPong wrote:

The C64's scheme is a classical scheme used on 6502 cpus of the era. Nothing special.
Basically it is a classical DMA implementation + the trick used to share 50% of the memory bandwidth without the need of bus arbitration. ...
Others processors required a more complex arbitration mechanics .

The C64 is a little special because the VIC-II has an internal buffer for the current tile row, which it fills on the first scan line of every row and then retains. So, demo-esque trickery aside, every eighth line it needs double the video bandwidth, for which it halts the CPU for between 40 and 43 cycles.

The Vic-20 is more like the standard scheme I think, of just using phase 2 to grab memory without interrupting the 6502 at all. Which is what the C64 does on the other seven lines of each row and during the border.

By PingPong

Prophet (3123)

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14-09-2018, 19:48

Quote:

The C64 is a little special because the VIC-II has an internal buffer for the current tile row, which it fills on the first scan line of every row and then retains. So, demo-esque trickery aside, every eighth line it needs double the video bandwidth, for which it halts the CPU for between 40 and 43 cycles.

the internal buffer is not a special feature rather a requirement. Otherwise the cpu will suffer too much of slow downs if the VIC-II have to halt too much .
When i talk of the worst case i also consider the time needed for every sprite scanline assuming 21 lines of 8 sprites on screen row-aligned. In that case the VIC-II need others 8x3 bytes=24bytes of extra delays so we have 40+24=64

By TomH

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14-09-2018, 22:02

PingPong wrote:
Quote:

The C64 is a little special because the VIC-II has an internal buffer for the current tile row, which it fills on the first scan line of every row and then retains. So, demo-esque trickery aside, every eighth line it needs double the video bandwidth, for which it halts the CPU for between 40 and 43 cycles.

the internal buffer is not a special feature rather a requirement. Otherwise the cpu will suffer too much of slow downs if the VIC-II have to halt too much .

The quoted text was "The C64's scheme is a classical scheme used on 6502 cpus of the era. Nothing special."

That establishes that 'special' here means 'unusual' — it is as contrasted with a "classical scheme".

The following contemporaneous of the era have no such internal buffer and no such pausing of the CPU, doing all work in phase 2:

  • the Apple II;
  • the BBC Micro;
  • the Oric; and
  • the C64's immediate predecessor, the Vic-20.

What the C64 does therefore is 'special' in the given meaning; it is different from the classical scheme, as used by almost all of its cohort.

I appreciate you can move the goalposts mid-conversation and argue that since it's straightforward it's not one of the other meanings of special, but have no opinion about that.

(EDIT: and the three other machines I can think of that stop a 6502 to get extra memory bandwidth — the Ataris, the Acorn Electron and the Atari Lynx — all do so by stopping the clock, not by using the RDY line, so the C64 doesn't even commonality with those)

By litwr

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14-09-2018, 22:26

@TomH Don't miss Commodore+4. It has the most interesting and advanced way to work with video. It has only 0.9MHz CPU but at border area where no video access is required it uses doubled frequency and this make it the fastest 8-bit Commodore. It can use 121 colors and this require 2 "bad lines" for each character row. I made a short video some time ago with Commodore+4 picture show - youtube link. BTW the prototype of this computer (Commodore-264) was going to be an MSX killer pricing $79 in 1984 but Jack Tramiel was fired and MSX survived.

By TomH

Master (216)

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14-09-2018, 22:57

Alas I've no awareness of the +4 hardware whatsoever; and I really, really don't mean to imply that the C64 is being clever, or is the best possible machine of its time/price. I also don't mean to imply that either of those things necessarily isn't true. Just that its bus, regardless of simplicity or any other axis of evaluation, is not the same as most similar machines.

Honestly, I'm not even sure I have a strong opinion about the SID versus the OPL. We're well outside of the realm of machines I have more than academic experience of at this point.

By PingPong

Prophet (3123)

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14-09-2018, 23:40

TomH wrote:
PingPong wrote:
Quote:

The C64 is a little special because the VIC-II has an internal buffer for the current tile row, which it fills on the first scan line of every row and then retains. So, demo-esque trickery aside, every eighth line it needs double the video bandwidth, for which it halts the CPU for between 40 and 43 cycles.

the internal buffer is not a special feature rather a requirement. Otherwise the cpu will suffer too much of slow downs if the VIC-II have to halt too much .

The quoted text was "The C64's scheme is a classical scheme used on 6502 cpus of the era. Nothing special."

That establishes that 'special' here means 'unusual' — it is as contrasted with a "classical scheme".

The following contemporaneous of the era have no such internal buffer and no such pausing of the CPU, doing all work in phase 2:

  • the Apple II;
  • the BBC Micro;
  • the Oric; and
  • the C64's immediate predecessor, the Vic-20.

What the C64 does therefore is 'special' in the given meaning; it is different from the classical scheme, as used by almost all of its cohort.

I appreciate you can move the goalposts mid-conversation and argue that since it's straightforward it's not one of the other meanings of special, but have no opinion about that.

(EDIT: and the three other machines I can think of that stop a 6502 to get extra memory bandwidth — the Ataris, the Acorn Electron and the Atari Lynx — all do so by stopping the clock, not by using the RDY line, so the C64 doesn't even commonality with those)

I disagree. In electronics what were done in C64 is called DMA. the 6502 was extended in 6510 in order to apply this schema (ability to go in high impedance from a DMA request). This is classical . The fact that there is a arbitration is not special in electronics, it's usual and is dictated by the relatively high bandwidth requirements of the VIC-II.

By contrast, the ZX Spectrum used a original solution (even if tricky) called floating bus. the side effect is that the z80 is not halted when accessing some ram region where there is no VRAM access.
This is a original ( and imho a little dirty and cheap ) solution. It's unusual in electronics to decouple bus lines via resistors.

To summarize: the c64 did this in the right way. So nothing original. Only the correct way

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