How is that possible?

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By sdsnatcher73

Paragon (1328)

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06-11-2020, 09:36

Indeed there are real Z80 and Z280 on the board. Z80 can be used as main processor, Z280 as coprocessor (but unclear how). Real Z80 was used to ensure timing compatibility. I wonder (just wonder) though if an FPGA Z80 based on the a-z80 would have been a better choice, the a-z80 has been reverse engineered by inspecting real z80 die photographs. So it is a z80 implementation that is identical to a real z80 to the transistor level, thus also ensuring same timing compatibility and even all undocumented features (and bugs) needed no extra work. That way adding the multiplication might be more easy?

By erpirao

Paragon (1116)

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07-11-2020, 21:49

In the last video I have recommended the demo calculus to do performance tests and the ray tracing demo of anarchy, but does anyone know where to get the latter?

By erpirao

Paragon (1116)

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29-11-2020, 16:08

By Grauw

Ascended (9486)

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29-11-2020, 23:29

Ah very interesting, I had seen the video but wondered how the performance was improved.

It seems that rather than running a “server” polling loop on the Z80, it now generates instructions for the Z80 on the fly. So e.g. the Z80 instruction fetch gets nop until an I/O output occurs, then it gets ld a,nn / out (nn),a. Clever! I think for input it can possibly directly snoop the return value off the bus? It also probably sometimes needs to output a jump to constrain the PC value…?

By erpirao

Paragon (1116)

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05-12-2020, 16:28

I have asked him in the video the possibility of adding an accelerator in the slt-turbo, what happens is that he did not explain me well.
his answer
This system provides parallel I/O execution to Host MSX. But it still requires original Z80 for external CPU.
In case of Z180, it cannot be used for MSX CPU due to an internal peripheral, which occupies 64 addresses.
This is why I chose Z280 as main CPU. It has 24BIT I/O address and its internal peripheral occupies high bank I/O (FExxxxh/FFxxxxh), which doesn't conflict with MSX's I/O.

By Pencioner

Scribe (1288)

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05-12-2020, 18:28

I just had a look to Z180 manual to check if i understood correctly. Apparently yes, there are on-chip periferals like DMA controller etc which are operated via I/O and utilize ports in the range 0-255 (while leaving 16 bit port numbers higher than 255 for periferals). That makes it incompatible, because any I/O on MSX device might result in unexpected changes of Z180 behaviour, and since they sit on the same bus - it will happen

By PingPong

Prophet (3586)

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05-12-2020, 18:52

@Grauw:this was my assumption when i asked how it was done. But previously how was working?

By Pencioner

Scribe (1288)

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05-12-2020, 19:16

Maybe it was implemented with a 'busy loop' on MSX side (which was put in some device bios code or so)

By erpirao

Paragon (1116)

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05-12-2020, 19:52

PingPong wrote:

@Grauw:this was my assumption when i asked how it was done. But previously how was working?

from sharksym`s blog , by google translate
Here is a summary of the difference in behavior between the initial version and the current version.

@ Early version
All code runs in host memory
Host CPU checks BUS status of SLT-Turbo and executes necessary routines

@ Current version
All codes run in SLT-Turbo slot
BUS Arbiter generates required code

The code space (address) of the host CPU is Page 0 (0000H ~ 3FFFH).
Anyway, because of interrupt processing, writing Page 0 will take up less space.
For reference, Page 1 and 2 are used for virtual slot mapping of SLT-Turbo. (Details will be explained later~ㅋ)
Page 3 keeps the host's memory intact. It is continuously used for DATA and Stack.

By PingPong

Prophet (3586)

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05-12-2020, 20:44

thx for explaining, but to be clear currently how does happen when the z280 is about to execute this?

test:
ld b,200
ld c,0x98
ld hl, 0x2000
otir

can some one describe in detail?

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