msx vaporware - true or false ?

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By flyguille

Prophet (3028)

flyguille's picture

09-01-2014, 23:44

hit9918 wrote:

Yes, noise can be aceptable, it depends on the graphics.

Look at this capture of a real NES, it too has a bit scroll noise:
http://www.youtube.com/watch?v=bTGEdfdz7xA

Look at for example the green bars. In case of NES it is something on the analog side of things.

noice can be used in favor, like some (volcanic fluid) running in some ground.

By hit9918

Prophet (2925)

hit9918's picture

09-01-2014, 23:53

@flyguille, there is no rule with 4 pixels blank, there is a rule with 7 pixels blank. Only in 4 pixel scroll there is some 4 pixels rule. Also manbow gfx did something with 4 pixels. But MSX1 scroll rules are different.

But then, e.g. in uridium scroll, there is bleed that looks like the zone is 4 pixels wide.
That again got connection to "the colorbytes can change in any scrollstep".

If colorbytes would only be set on scrollstep 0, like if you only got 1 set of colorbytes for all 8 scroll positions, then the bleed zones would be double wide.

Malaika gfx is in that lesser mode like it would have only one set of colorbytes. But a vram cache is forced to have 8x colorbytes anyways, it is not a memory size problem. When only 1x gfx is in ROM, need apropriate algorithm to calculate the 8 scrollsteps of the bigger mode.

Maybe that too should be mentioned: gfx without noise needs to be in ROM only one time and could be extracted to 8x later.

By hit9918

Prophet (2925)

hit9918's picture

09-01-2014, 23:49

p.s. but then the machine needs enough RAM to hold 8x charset.

By hit9918

Prophet (2925)

hit9918's picture

10-01-2014, 00:23

Oh, and the turrijump demo does 8 pixel scroll vertical. A trick, the vertical scroll is started when the feet hit the ground.
It looks natural, a bit like getting out of focus of the cam when suddenly changing speed. I have seen similar pattern in ghost n goblins arcade! Smile
here: http://www.youtube.com/watch?v=uIhyjrXVhzg&t=3m40s

By ARTRAG

Enlighted (6862)

ARTRAG's picture

10-01-2014, 00:58

flyguille wrote:

yes, because using the forecolor X full resolution it makes no noticeable that the common back color is limited to change only after a 4px blank.

that demo is 1px scroll? right?, so you needs 8 banks * 4096 * 3 (legacy screen2)

so all the work is updating the name table?, only if it was scrolleable horizontally only. And want to be limited to 16 unique tiles? 16x16=256 Big smile

now for including the vertical scroll, you needs to use screen2 as BASIC uses it, and updating the pattern and color table!.

4096 bytes?, 25fps without doing anything more?

No, you are on the wrong way on the whole line.
1) Color bleeding looks limited by the fact that mixing colors are similar, my screen 2 converter uses dithering and the speed of the scroll masks the color errors.
2) The Nemesis demo fits in just 256 tiles, so not a single tile definition is changed during scrolling. The demo uses by far more than "basic" 16 tiles (IIRC about 64). The key is in the number of transitions between adjacent tiles
3) Also for vertical scrolling, all depends on the transitions. You can have levels fitting in 256 tiles and levels that need more tiles. usually it is sufficient to update one or two tiles per frame to have almost everything you want on the screen.
This demo updates 0,7 tiles per frame, this other demoabout 2 tiles per frame.
Obviously, even updating a couple of tiles per frame, the framerate stays at 50/60 fps.

By flyguille

Prophet (3028)

flyguille's picture

10-01-2014, 01:34

separation transitions for vertical and horizontal axis sound likes the engine is ideal por a scrollable "maze" game (top view)!., where the transitions is the monocolored ground, and bushes are the walls.

By ARTRAG

Enlighted (6862)

ARTRAG's picture

12-01-2014, 16:25

Better for horizontal scrolling where you can use 512 tiles per page

By ARTRAG

Enlighted (6862)

ARTRAG's picture

19-01-2014, 10:49

As this project is on hold, this is the source with the trick that allows to have, in screen 2, two pages of 256x128 pixels for double buffering with 32 active sprites. It will work on any TMS bypassing the HW bug that causes sprite cloning.

The Pattern Generator Table of page 0 is at 2800h and 3000h (256+256 definitions)
The Color Table of page 0 starts at 0000h (just 256 definitions shared between the two banks)

The Pattern Generator Table of page 1 is at 0800h and 1000h (256+256 definitions)
The Color Table of page 1 is at 2000h (256 definitions shared between the two banks)


	output URIDx2.rom

	defpage	0,0x4000, 0x2000		; page 0 contains main code + far call routines
	defpage 1,0x6000, 0x2000		; static code 
	defpage	2,0x8000, 0x2000		; static code
	
	defpage	3,0xA000, 0x2000		; swapped data level0
	defpage	4,0xA000, 0x2000		; swapped data level1
	defpage	5,0xA000, 0x2000		; swapped data level2
	defpage	6,0xA000, 0x2000		; swapped data level3
	
	defpage	7,0xA000, 0x2000		; swapped data new tiles
	defpage	8..15




	macro setVdp register,value       ; macro definition
	di
	ld	a,value
	out	(0x99),a
	ld	a,register
	or	0x80
	out	(0x99),a
	ei
	endmacro
  
; -----------------------------
; smooth scroller demo
; Trilobyte 2014
; ------------------------------

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;   Mapper Konami 5 (mapper +  scc)
;
; Bank 1: 5000h - 57FFh (5000h used)
; Bank 2: 7000h - 77FFh (7000h used)
; Bank 3: 9000h - 97FFh (9000h used)
; Bank 4: B000h - B7FFh (B000h used)

; *** CONSTANTS ***
_bank1			equ	0x5000
_bank2			equ	0x7000
_bank3			equ	0x9000
_bank4			equ	0xB000

_PCT:			equ	0x0000
_PGT:			equ	0x2000

include variables.asm

LvlWidth:		equ	nf/4+32

; *** RAM ***

	map 0xc000

pane0:			#768  
pane1:			#768
buffer:			#1024

slotvar:		#1
slotram:       	#1

msxtype			#1
palette			#1

vsf:			#1
cnt:			#1
muteflag:		#1

SLOT            #1
PAGE1RAM        #1
RAMSLOT         #1

SCC				#1
SUB             #1

xmap			#2
curframe		#2
pgtbase			#2
pctbase			#2

	endmap

; *** PNT datain rom ***

	page 3
level0:
	include pntdata\level_0.asm
	page 4
level1:
	include pntdata\level_1.asm
	page 5
level2:
	include pntdata\level_2.asm
	page 6
level3:
	include pntdata\level_3.asm
	

; ------------
; megarom header

	page 0
	code page 0
	
	org	04000h
	db	041h,042h
	dw	initmain
	dz 	'TRI004'
	ds	5

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vdp access

_vdpReg equ 0xF3DF
LINL40	equ 0xF3AE

; e = screen mode
_scr:
	ld	a,(_vdpReg+1)
	or 2
	ld	(_vdpReg+1),a
    di
	push ix
	push iy

	ld	a,40				; useful when going to screen 0
	ld (LINL40),a	

	ld a,e
	ld iy, ((0xfcc0 - 1))
	ld ix, 0x005f
	call 0x001c
		
	pop iy
	pop ix
	ei
	
	di					;	setvdpwvram(0x1800);
	xor	a				
	out (0x99),a
	ld	a,0x18+0x40
	out (0x99),a
	ei
	xor a				;	clear top panel
	ld	bc,0x0098
1:	out (0x98),a
	djnz	1b
	ret
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; a = value
; e = register
_setvdpreg:
	di
	out (0x99),a
	ld	a,e
	or	0x80
	out (0x99),a
	ei
	ret
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; de = map pointer
;	a = map page
_plot_pnt:
	ld	(_bank4),a
	ld	hl,(xmap)
	add	hl,de
	ex	de,hl

	di					;	setvdpwvram(0x1800+256);
	xor	a
	out (0x99),a
	ld	a,0x19+0x40
	out (0x99),a
	ei
	ld	a,16
	ex de,hl
	ld	c,0x98
newline:		
	repeat 32
	outi
	endrepeat
	
	ld	de,LvlWidth-32
	add	hl,de
	
	dec	a
	jp	nz,newline
	ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;          defb 0x02 ; Reg# 0 000000[M3][EV]
;          defb 0x62 ; Reg# 1 [4/16k][BLANK][IE][M1][M2]0[SIZE][MAG]
;          defb 0x06 ; Reg# 2 0000[NAME TABLE BASE ADDRESS]          = 1800h

;          defb 0x9F ; Reg# 3 [COLOR BASE ADDRESS]                   = 2000h ; hybrid mode for colors
;          defb 0xFF ; Reg# 3 [COLOR BASE ADDRESS]                   = 2000h ; regular mode for colors	

;          defb 0x1F ; Reg# 3 [COLOR BASE ADDRESS]                   = 0000h ; hybrid mode for colors
;          defb 0x7F ; Reg# 3 [COLOR BASE ADDRESS]                   = 0000h ; regular mode for colors	
	  
;          defb 0x00 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS]  = 0000h ; hybrid mode for patterns
;          defb 0x03 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS]  = 0000h ; regular mode for patterns

;          defb 0x04 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS]  = 2000h ; hybrid mode for patterns
;          defb 0x07 ; Reg# 4 00000[PATTERN GENERATOR BASE ADDRESS]  = 2000h ; regular mode for patterns
          
;          defb 0x36 ; Reg# 5 0[SPRITE ATTRIBUTE TABLE BASE ADDRESS] = 1b00h
;          defb 0x07 ; Reg# 6 00000[SPRITE PTRN GNRTR BASE ADDRESS]  = 3800h
;          defb 0x01 ; Reg# 7 [TEXT COLOR 4bts][BACKDROP COLOR 4bts]


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
disp_page1:			; page 1 active
	setVdp 3,0x9F	; 	colours at 0x2000	(hybrid)
	setVdp 4,0x03	;	patterns at 0x0000	(regular: used 0x0800 0x1000)
	ret

disp_page0:			; page 0 active
	setVdp 3,0x1F	; 	colours at 0x0000	(hybrid)
	setVdp 4,0x07	;	patterns at 0x2000	(regular: used 0x2800 0x3000)
	ret	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; write page 1
write_page_1:
	ld	hl,0x2000
	ld	(pctbase),hl	; write colours at 2000h
	ld	hl,0x0800
	ld	(pgtbase),hl	; write pattern at 0800h & 1000h
	call tileupdate

	ld	hl,(curframe)
	ld	bc,6			
	add	hl,bc
	ld	(curframe),hl
	ret
	
; write page 0
write_page_0:
	ld	hl,0x0000
	ld	(pctbase),hl	; write colours  at 0000h
	ld	hl,0x2800
	ld	(pgtbase),hl	; write pattern at 2800h & 3000h
	call tileupdate
	
	ld	hl,(curframe)
	ld	bc,6			
	add	hl,bc
	ld	(curframe),hl
	ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ROM initialisation

initmain:

	ei
	halt
	di

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; set pages and subslot
;
	call    0x138
	rrca
	rrca
	and     0x03
	ld      c,a
	ld      b,0
	ld      hl,0xfcc1
	add     hl,bc
	or      (hl)
	ld      b,a
	inc     hl
	inc     hl
	inc     hl
	inc     hl
	ld      a,(hl)
	and     0x0c
	or      b
    
	ld      h,0x80
	call    0x24  
	
	; now we have:
	; page 0 	- bios
	; page 1,2	- megarom mapper
	; page 3	- RAM
	
	; init megarom mapper
	xor	a
	ld	(_bank1),a
	inc	a
	ld	(_bank2),a
	inc	a
	ld	(_bank3),a
	inc	a
	ld	(_bank4),a
	
	; now the first 32KB of the megarom are active

	;clear 8K RAM
	ld	bc,1024*8-1
	ld	hl,0xc000
	ld	de,0xc001

	ld	(hl),0
	ldir	
	
	call resetscroll
		

;;;;;;;;;;;;;

scrollinit:
	
	call	set_spts
	
	;	show page 0
	call disp_page0

	; 	load tileset for frame 1
	;	write page 1
	
	call	write_page_1

;;;;;;;;;;;;;
	
main_loop:

;;;;;;;;;;;;;
[1]	halt

	;	show page 1
	call disp_page1
	
	; show frame 1	
	ld	a,:level0
	ld	de,level0

	call _plot_pnt

	; 	load tileset for frame 2
	;	write page 0
	call	write_page_0

;;;;;;;;;;;;;	
[1]	halt

	;	show page 0
	call disp_page0

	; show frame 2	
	ld	a,:level1
	ld	de,level1
	call _plot_pnt

	;	load tileset for frame 3
	;	write page 1
	call	write_page_1
	
;;;;;;;;;;;;;
[1]	halt

	;	show page 1
	call disp_page1

	; show frame 3	
	ld	a,:level2
	ld	de,level2
	call _plot_pnt

	;	load tileset for frame 4
	;	write page 0
	call	write_page_0
		
;;;;;;;;;;;;;
[1]	halt
	
	;	show page 0
	call disp_page0
	
	; show frame 4	
	ld	a,:level3
	ld	de,level3
	call _plot_pnt

	;	load tileset for frame 5
	;	write page 1
	call	write_page_1
	
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	
	call scrollstep
	
	jp main_loop
	
	ret
	
scrollstep:
	ld	hl,(xmap)
	inc	hl
	ld	(xmap),hl

	ld	a,l
	cp	nf/4

	ret	nz

resetscroll:
	ld	hl,0
	ld	(xmap),hl
	ld	hl,pages
	ld	(curframe),hl
	
	setVdp 7,8
	ld	e,2
	call _scr
	setVdp 7,1

	pop	af
	jp scrollinit

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; critical
;
; update the tiles for of current frame
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

tileupdate:
	ld	a,:pages
	ld	(_bank4),a

	ld	hl,(curframe)
	ld	a,(hl)
	and	a

	ret	z				; number of tiles to be updated
	
	ld	b,a
	inc	hl

	ld	a,(hl)			; bank where data are
	inc	hl
	ex af,af'

	ld	c,(hl)
	inc	hl
	ld	a,(hl)
	inc	hl				; point to the list of tile numbers (VRAM positions)
	
	ld	e,(hl)
	inc	hl
	ld	d,(hl)			; points to the list of actual pgt/pct data
	
	ld	l,c
	ld	h,a
	ex af,af'
	ld	(_bank4),a		; set the bank with pct/pgt data 
	
; hl points to the list of tile numbers
; de points to the pgtdata/pctdata
; b holds the number of tiles to be updated

; in bank4 there are the pgtdata/pctdata and the list of tile numbers

	ld	c,0x98

	push de

	push bc
	push hl
	
1:	push bc
	push de
	ld	de,(pgtbase)
	call 	setvramaddr
	pop		de
	ex	de,hl
[8]	outi
	ex	de,hl
	pop	bc
	djnz	1b

	pop	hl
	pop	bc
	pop	de

	push	bc
	push	hl
	
1:	push bc
	push de
	ld	de,(pgtbase)
	ld	a,0x08
	add	a,d
	ld	d,a
	call 	setvramaddr
	pop		de
	ex	de,hl
[8]	outi
	ex	de,hl
	pop	bc
	djnz	1b
	
	pop	hl
	pop	bc
	
1:	push bc
	push de
	ld	de,(pctbase)
	call 	setvramaddr
	pop	de
	ex	de,hl
[8]	outi
	ex	de,hl
	pop	bc
	djnz	1b

	ret

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;	convert a VRAM position pointed by HL 
;	in a VRAM address with offset in DE
;	sets the VDP for write
;	in:
;		HL -> VRAM Position
;		DE = VRAM Offset
;	out:
;		HL++

setvramaddr:
	ld	a,(hl)
	push hl
	ld	l,a
	ld	h,0
	add	hl,hl
	add	hl,hl
	add	hl,hl
	add	hl,de
	ld	a,l
	di
	out	(0x99),a
	ld	a,h
	or	0x40
	out	(0x99),a
	ei
	pop	hl
	inc	hl
	ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;	place 32 sprites

set_spts:
	halt
	di					;	setvdpwvram(0x1B00);
	xor	a				
	out (0x99),a
	ld	a,0x1b+0x40
	out (0x99),a
	ei
	ld	hl,test_sat
	ld	b,128
	ld	c,0x98
	otir
	di					;	setvdpwvram(0x3800);
	xor	a				
	out (0x99),a
	ld	a,0x38+0x40
	out (0x99),a
	ei
	ld	hl,test_spt
	ld	b,32
	ld	c,0x98
	otir
	ret


test_sat:
	repeat	8
	repeat	4
	db	@@# * 24
	db	48+@# * 32+@@#*8
	db	0
	db	15
	endrepeat
	endrepeat

test_spt:
	repeat	16
	db	0xAA
	db	0x55
	endrepeat
	
	
	include	"includeall.asm"

By ARTRAG

Enlighted (6862)

ARTRAG's picture

07-02-2014, 08:38

@hit9918

Just to let you know I'm still at least thinking to this project. This is the draft of the optimization algorithm for fitting the two tile sets (upper and lower sets) in one single color table.
As told before, the idea is that if a tile in the one set has one or more lines equal to 00000000b or to 11111111b, those lines can have any color for 1's or for 0's (as these latter colors are not shown). The colors of lines equal to 0 and to 255 are non fully specified and the tile can be shown using any of the colour profiles "compatible" with the sole specified part of the attributes.
Thus, changing the colors of the non specified attributes, a tile in the upper set can be made compatible with other tile in the lower set that has the same colors in the lines completely specified and one of the "compatible" colors in the lines that in the other tile are non fully specified.

This is the draft matlab script in natural language...

function [ newTilesu,newTilesd,PCT,PGTu,PGTd ] = optimize_colors( chru,chrd,clru,clrd, Tilesu,Tilesd )
%optimize_colors: two tile sets are rearranged in order to share the same colour definitions

% for each character in the upper set, create a set of equivalent colours
%i.e.
% for each line == 0xFF
% create 15 colour profiles with colours 0xZ1,0xZ2,0xZ3...0xZF in that line,
% where Z is the initial colour attribute for '1'
% for each line == 0x00,
% revert it to 00 and create 15 colour profiles with colours 0xZ1,0xZ2,0xZ3...0xZF
% where Z is the initial colour attribute for '0'
%
% for each character in the lower set, create a set of equivalent colours
% same as above
%
% at this point each tile in the two sets as one shape definition and a set
% of compatible colour definitions
%
% let be setmax the character set with less characters and setmin the other
% be setmax' = setmax
%
% for each x character in setmax'
%
% found = 0
% for each y character in setmin
% t = intersect (colourset_x,colourset_y)
% if t is not null, found = 1 break search
% next y
%
% if found==1
% remove y from setmin
% remove x from setmax
% place x and y in the two tile sets
% place t in the colour set
% endif
% next x
%
% now in setmin and in setmax we have tiles that cannot match anything
% store setmax in the tile set in spare positions
% store setmin in the tile set in spare positions

This should be the best we can get to pack tiles in VRAM with limits of this odd screen mode...
Any better idea ?

By hit9918

Prophet (2925)

hit9918's picture

07-02-2014, 14:49

I am not sure about the code.
one got to take care to not think the way one is used to in RAM/ROM where with pointers can wildly share things.
vram sharing is more limited, two patterns can share one color. if they are in separate screen regions

if a char is only used in top area, then in bottom area this char number is free for another char.
the char to be searched must be unused in top area.
and if it still looks same with the other color, things can be collapsed to one char number.

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