Need your opinion regarding GR8NET capabilities

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By Grauw

Enlighted (8189)

Grauw's picture

09-09-2015, 20:39

You’re interpolating the SCC? Not a fan of that, it changes the characteristic of the SCC too much IMO.

Not saying it can’t sound nice (though perhaps a bit too clean to some people’s tastes), but it makes the SCC music sound different from how it was originally intended to sound.

Compare original vs interpolated Gradius 3 intro. [Edit: oops, fixed link.]

My 2¢.

By Eugeny_Brychkov

Paragon (1079)

Eugeny_Brychkov's picture

09-09-2015, 23:34

It's easy to see. Give me ROM image, I will try.

Edit: I tried the ROM. No, I do not do interpolation. Sound output goes as expected with 3.58 MHz speed.
I would say my sound is something in the middle of these two. High freqs from original SCC are preserved, but sound seems to be clearer on lows. Actually great thanks to Konami for making good samples!

By Grauw

Enlighted (8189)

Grauw's picture

10-09-2015, 00:09

Aha, I see.

The interpolation I did in the sample above scaled up the waves from the usual 32 8-bit samples to be 1024 16-bit samples, linearly interpolated (so some high frequencies are still present, the “perfect” upscale would be by using an FFT transform). If you don’t do interpolation, which part is 16-bit then? Just the DAC, but still receiving padded 8-bit values? I could see how a proper DAC would give better audio quality than a simple resistor array…

I’m curious about the sound now, could you perhaps record a comparison? (If it’s not too much trouble, just curious.)

By Eugeny_Brychkov

Paragon (1079)

Eugeny_Brychkov's picture

10-09-2015, 00:16

I am afraid I do not have good recording equipment Sad

Well, actually I said 16-bit and that is not fully correct, and you see it of course. Technically I multiply 8-bit wave data onto 4-bit volume, getting 12-bit signed integer, and then add data for 5 channels, which is 15 bits max. But to have sound in line with PSG, I multiply not onto 4 bit volume, but this volume multiplied by 4. Thus at the SCC output I have register larger than 16 bits, and I did not "hear" any 16-bit overflows so far. I had mechanism to prevent saturation in SCC, but then moved this mechanism onto the final DAC register management.

By hit9918

Prophet (2855)

hit9918's picture

10-09-2015, 03:03

yes, the unfiltered scc is better.
and there was some bug like the the output is sample OR previous sample.
maybe that screams even more like the original.
how about two modi, quality mode and SCC screaming Smile

By maxis

Champion (512)

maxis's picture

10-09-2015, 15:23

Hello,

Originally the SCC cartridge sound goes via the MSX motherboard audio mixer. This audio mixer has a built in low pass filter in EVERY MSX computer. The cut off frequency is in between 18-22KHz. So, having the output DAC sampling frequency at 3.58MHz or 48KHz wouldn't make any difference for the standard audio implementation. On top of that, R2R matrix has non-zero output impedance and SCC doesn't have an intermediate audio amplifier. Also the MSX mixer input impedance varies from one computer to another. Hence the transfer function of the audio path will vary from one computer to another too.
Bottom line - IMHO, it is difficult to achieve the repeatable or the "standard" audio performance of the original MSX SCC cartridge.

Here you can listen the Proycon 20bit audio DAC output pushing SCC+PSG+PPI content:

Parodius. Procyon 20bit@48KHz audio
Recorded via Procyon TOSLINK fiber optical output

And here you can listen to the emulated audio:
Parodius. BlueMSX

Comparison goes with all the audio compression artifacts as usual :)

@Eugeny_Brychkov I would suggest to do the dynamic range test of your system. You can register 1KHz 16 bit sine wave into the ROM and then play it back and record with a good enough audio card (>102 dB of dynamic range). Then perform the FFT with any window function. Check the noise floor (this is you actual dynamic range) and spurs. More/bigger spurs you have - higher the THD you will have at the end.

By Eugeny_Brychkov

Paragon (1079)

Eugeny_Brychkov's picture

10-09-2015, 16:00

Maxim, excellent analysis, thank you.
You confirm that output DAC frequency should not be less that 22k to achieve the result across the MSX family. Note that it is about sampling frequency, actual serial data clock will run much faster, and even faster than 3.58 MHz.
I used scope on the 16-bit R2R with saw-shaped pulses, and due to non-linearity and noise decided to discontinue R2R, it missed expectations on the low end of the frequency scale, and generally there're calculations proving that R2R above 12 bits will introduce audible distortion to the waveform.

By maxis

Champion (512)

maxis's picture

10-09-2015, 17:50

Hello, Eugeny,

IMHO, you don't have to maintain such a high sampling rate at all. This would simplify your solution.
On the other hand, the Nyquist frequency needs to be above the LPF cutoff frequency of the aforementioned audio mixer. So, the sampling rate is the double of the Nyquist frequency, hence the minimum will be about 44 KHz. I've tried 48, 96 and 192 KHz sampling rate and couldn't see on the spectrum analyzer any difference. Maybe the "golden ears" would hear things?
Therefore, I've limited the sampling rate to 48KHz after applying the downsampling/antialiasing filter in the FPGA.

Also wanted to point out some more reasons why R2R matrix is not precise:
1. Deviation in resistor values
2. We don't actually use the calibrated current keys in the output IC, but rather uncalibrated digital outputs. This is fine for 8 bits and even 9 bits, but not more.
3. The switching time of the outputs is not simultaneous, therefore generates false codes -> the commutation spikes.
4. R2R is not connected to the current input intermediate buffer/filter with the low output impedance (it is called TIA - transimpedance amplifier), therefore non-linear performance (what you have observed).

So, your choice to drop R2R I do entirely support. Also it is better using Sigma-delta DAC instead of FLASH parallel DAC due to the missed codes, high spurs and high non-linearity in the latter. And audio DACs do incorporate the reconstruction/anti-aliasing filters.
I've chosen using the standard AC97 PC motherboard ADC/DAC, which has a very decent performance - CS4205 and then I've moved to CS4202 and now quite satisfied with the results.

Thank you.

By Eugeny_Brychkov

Paragon (1079)

Eugeny_Brychkov's picture

10-09-2015, 17:56

Updated the manual. Please pay attention to parts 5 and 6 (pages 30-56). Any constructive feedback is welcome.

By Eugeny_Brychkov

Paragon (1079)

Eugeny_Brychkov's picture

10-09-2015, 18:08

maxis wrote:

you don't have to maintain such a high sampling rate at all. This would simplify your solution.

Internal clock is running 112.5 MHz, thus slower speed actually increases complexity and uses more registers Smile

maxis wrote:

I've limited the sampling rate to 48KHz

DAC chip is running sampling frequency slightly higher than 44.1kHz (just because it is simple using abovementioned clock frequency)

maxis wrote:

So, your choice to drop R2R I do entirely support.

Thank you. So big R2R was first try, giving some good experience I'll never forget LOL!

maxis wrote:

I've chosen using the standard AC97 PC motherboard ADC/DAC

I use UDA1334BTS. It's easy to source and satisfies technical requirements.

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