I have uploaded a first draft attempt able to use the first SCC chip found on the machine.
Look for the version adapted to sjasm 042c, it should look for SCC chips in all slots and subslots and use the one found in the lower slot in the system.
If you want to hear a chip different from the one on the flash cartridge, put the flash cartridge with the code in slot 2 and the SCC chip to be tested in slot 1.
https://sites.google.com/site/testmsx/Home/scc-pcm-replayer?...
As before use only NTSC machines.
Let me know if it works and, in case, with which configuration it fails to select the SCC.
[EDIT]
I added also an ascii-8 version that works only with an SCC in the other slot, this to avoid any confusion ;-)
With timed delays one could have 64 byte samples and ordinary 32 byte samples getting hardware smoothened, how about that as a tracker feature
it needs just one feature
delay64
a channel is delayed to the neighbour channel, play the same note in two channels, and there we go.
with that one mechanism, the artist can pick various shemes anytime in the song
2 voices with 64 byte samples
1 voice 32 byte sample hardware smoothened, 3 normal voices
1 voice 64 byte sample, 1 voice 32 byte sample hardware smoothened, 1 normal voice
1 voice 64 byte sample, 3 normal voices (2 voices share wave)
for future tricks with octave chords or USAS 1:3 chords and the habit to put the base tone in the left column,
the delay sheme should go from right to left:
write channel 5
delay channel 4 write by the time determined by channel 4 frequency register
delay channel 3 write by the time determined by channel 3 frequency register
...
then the feature got to be selected on the left of two columns.
and with delay96 (1/3 time of a sample byte) one could have
1 voice 96 byte sample, 2 normal voices with same wave
1 voice 32 byte sample extra smooth, 2 normal voices with any wave
and delay128 for 128 byte samples. or just another mode for the artist to try tricking with.
because one can select the wrong delay value and see whether it sounds interesting.
and delay0 to turn the feature off, save cpu time.
add new soft tones on the SCC
Polyphase decomposition of the signal is by far more efficient, as the cpu waits only 1/N of the final sampling time (where N is the number of channels). It holds also if you use 2 channels instead of 4
Read the thread pointed by Grauw.
Yeah two channels, delay time of halve a sample byte.
[] [][] [][][] + [] [][] [][][] = [ [[ [[[ [[[[ [[[[[ [[[[[[
the wording "delay64" was meant to be on the user level.
the artist picks the "delay64" command to use 64 byte samples or to soften oridinary 32 byte samples.
It works out of the box with all existing 32 byte samples.
All it takes is delays of frequency register writes (no reloading of the waves, no other ado)
low hanging fruit for a tracker to get a whole new SCC.
If you mean you want to offset of half a sample the two channels it is what the replayer does
Yes wave phase reset when writing frequency is a deformation register option. Also the sample counter resets when writing the frequency on real SCCs (causes slight distortion in pitch bends), but not on most FPGA SCCs. So you can also use that to delay by half a sample.
How to reset the phase of the channels on scc+?
On scc it is sufficient to write the period, is there a solution for other scc chips?
Hm, you’re right, the phase reset function of the deformation register doesn’t work on SCC+, I just tried in Synthesix.
I didn’t know that! Guess we shouldn’t rely on that feature…
[Edit: Never mind, the SCC+ deformation register is at a different address, even in SCC compatibility mode.]
Playing a sine tone of around 160Hz on Synthesix with the phase reset enabled (wave 1, phase r -0):
Phase reset happens at 60 Hz.
F1 Spirit SCC (deform register at E0H):
Snatcher SCC+ (deform register at C0H in both SCC & SCC+ modes):
MegaFlashROM SCC+ SD (deform register at E0H, at least in SCC mode, didn’t try SCC+ mode):
My fault. The deformation register is at a different position on scc and scc+
But phase reset at frequency write seems to work (at least on openmsx).
I solved by doing
ld a,00100000b ; Reset phase when freq is written ld (98E0h),a ; on SCC ld (98C0h),a ; on SCC+ in SCC mode
Yes indeed, same in Synthesix. Even in SCC mode, the SCC+’s deformation register is not at a compatible location. I forgot that I didn’t take care of that detail since I wrote it .
I’ve updated the picture above, now they look nice and similar.