CAS signal in SVI 738 or MSX in general

By lkpalwa

Expert (79)

lkpalwa's picture

18-04-2019, 13:33

I am trying to design a internal 256KB mapper solution for the SVI 738, now to question about ULA chip IC35 that provides RAS/CAS and MPX (MUX) signal, if used in a mapper do you need to modify CAS signal.
If I look into schematics for Yamaha YIS 503 they use the CAS2 signal and used OR signal to different CAS pin in dram chips?
If I look at expert they just compose signal using SLTRAM/MRQ-R abd MUX + R-MRQ to create CAS ?
R-MRQ and MRQ-R are build with RFSH and MREQ signal
So the question is can I use the CAS direct from ULA or do I need to try to rebuild it ???

The Yamaha have a S3527 engine so they use the CAS2 - is why the use some extra logic ??? because CAS2 and CAS3 have different range ?? NAND used here to select both ??

Also a more generic question in some mapper a LS125 is used for D0-D7 but in expert3/2 and MSX Data Pack volume 1 for mapper the D0-D7 are not handle that way - is a good or bad design to use a LS125 for the D0-D7 .. see for example the YAMAHA DIY mapper image :) or the JIPE mapper

thx in advanced :) :) :)

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By lkpalwa

Expert (79)

lkpalwa's picture

18-04-2019, 13:36

here are som images from expert2/3 (yellow schematics) and Yamaha DIY (white schematics)

By lkpalwa

Expert (79)

lkpalwa's picture

18-04-2019, 16:26

some info from IBM about DRAM

There are only a few signals that control the operation of a DRAM.
Row Address Select (Strobe) (RAS) The RAS circuitry is used to latch the row address and to initiate
the memory cycle. It is required at the beginning of
every operation. RAS is active low; that is, to enable
RAS, a transition from a high voltage to a low voltage level is required. The voltage must remain low
until RAS is no longer needed. During a complete
memory cycle, there is a minimum amount of time
that RAS must be active (tRAS), and a minimum
amount of time that RAS must be inactive, called the
RAS precharge time (tRP). RAS may also be used to
trigger a refresh cycle (RAS Only Refresh, or ROR).
Column Address Select (Strobe) (CAS) CAS is
used to latch the column address and to initiate the
read or write operation. CAS may also be used to
trigger a CAS before RAS refresh cycle. This refresh
cycle requires CAS to be active prior to RAS and to
remain active for a specified time. It is active low.
The memory specification lists the minimum amount
of time CAS must remain active (tCAS) to initiate a
read or write operation. For most memory operations, there is also a minimum amount of time that
CAS must be inactive, called the CAS precharge
time (tCP). (An ROR cycle does not require CAS to
be active.)
Address The addresses are used to select a memory location on the chip. The address pins on a
memory device are used for both row and column
address selection (multiplexing). The number of
addresses depends on the memory’s size and organization. The voltage level present at each address
at the time that RAS or CAS goes active determines
the row or column address, respectively, that is
selected. To ensure that the row or column address
selected is the one that was intended, set up and
hold times with respect to the RAS and CAS transitions to a low level are specified in the DRAM timing
specification.
Write Enable (WE) The write enable signal is used
to choose a read operation or a write operation. A
low voltage level signifies that a write operation is
desired; a high voltage level is used to choose a
read operation. The operation to be performed is
usually determined by the voltage level on WE when
CAS goes low (Delayed Write is an exception). To
ensure that the correct operation is selected, set up
and hold times with respect to CAS are specified in
the DRAM timing specification.
Output Enable (OE) During a read operation, this
control signal is used to prevent data from appearing
at the output until needed. When OE is low, data
appears at the data outputs as soon as it is available. OE is ignored during a write operation. In many
applications, the OE pin is grounded and is not used
to control the DRAM timing.

Smile Smile Smile

By RetroTechie

Paragon (1510)

RetroTechie's picture

18-04-2019, 21:00

As I've said so often with questions like this: if you need to ask how to do this, you probably shouldn't. Chances are good you'll end up with a non-working machine. "First understand, then build"

That said: easiest way would be to use static RAM. For example a 512K*8 bit SRAM. That avoids all the difficulties of DRAM control.

If you're going for an internal RAM expansion, why all the trouble for just 256K? Go for 512KB (SRAM), 1MB (2x SRAM, or a pair of 1M*4 bit), 2MB (a 4-high stack of SRAMs), or max it out (a pair of 4M*4 bit). Practically the same amount of work...

If you use a pair of *4 bit DRAMs, you can most likely re-use /RAS and /CAS as-is. Buuuttt... depending on how these signals are timed, an external refresh address may be needed. 64K(bit) DRAMs usually have a 128-cycle refresh that is supplied by the Z80, bigger DRAMs with eg. a 256- or 512-cycle refresh address may need addition of a counter that supplies the extra bits. Would that be needed? Unknown, as there's no datasheet for that ULA IC35. If needed, you have the choice between adding such a counter, or... generate /RAS and /CAS yourself in such a way that the DRAM uses an internally generated refresh address.

Which brings me back to "use SRAM to avoid all this trouble". Btw there exist 1M*8 and even 5V-powered 2M*8 SRAMs these days, but they come in difficult-to-work-with packages (besides being hard to find).

By lkpalwa

Expert (79)

lkpalwa's picture

18-04-2019, 23:48

Yes but I will just use 2 x 44256 DRAM and try to keep it simple - all glue logic are TTL LS chips that will be replace by CPLD
I try to solve the SVI expansion clue - Henrik Gilvad successfully upgrade alot of does machines from 256 to 1MB so it possible but no info exist Sad

I will try to keep on solving the clue ... I know alot of user have upgrade there machine to MSX2+, so could I solved this I will publish the schematics, and order som PCB for does that do not want to make the hack themselfs Smile

The plan is to remove LS157 + 8 dram (original 64kb) and reuse signal from does pins to the addon card Smile Smile Smile

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