CPLD designing in progress...

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By RetroTechie

Paragon (1563)

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13-07-2010, 22:51

Made some significant progress with my CPLD experiments:

  • Gathered a good set of reference documents on Verilog & VHDL. There are lots of short intro's / tutorials out there, but good reference books are a lot harder to find. It's clear most of this stuff is targeted at professional designers that don't mind paying $ 100+ for a good language reference. And 'open standards': sure, as long as you don't mind paying standards organization like IEEE for a copy (=expensive), or get buy with books based on said standards (which are probably easier to read than those standards, but that's beside the point).
  • Worked through the Xilinx ISE in-depth tutorial (all chapters). For anyone considering getting into programmable logic: highly recommended! You basically only need diskspace (no development board required, but a large monitor is helpful), and it gives you a good idea of what's possible / the many steps from idea -> programmed device. In a sense it's a bit like PCB design, not with IC's/pins/circuit traces, but with 'virtual' logic circuitry inside IC's. Many nice-looking screenshot opportunities. LOL! (for pure software ppl: this stuff is probably not for you).
  • Saw many Verilog & VHDL snippets in the course of that tutorial. Too early to say I can program in either, but reading Verilog or VHDL sources & understand what happens, is getting easier!
  • Got my 1st self-designed circuit, with self-chosen I/O pins, onto my CPLD board (a basic inverter, on the board a flashing LED). Done in about 20 minutes using schematic entry. Of course a tiny circuit, but this represents a big milestone for somebody who's never done a CPLD design before. Smile

So basically I've reached the point where I could cook up a circuit from scratch & make a CPLD do that circuit's function. Big smileBig smile

Next up: some random logic experiments to become a little more comfortable with the design flow / software.

Considering to do an MSX memory mapper (shouldn't be too hard). Any suggestions for things to try are welcome, as long as it's simple circuits (what you could put together with a couple ~ a dozen 74xx IC's).

--
Bitcycle.org - just flipping bits

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By mohai

Paladin (932)

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14-07-2010, 20:42

I had in mind to desing a character pattern generator for the V9938/V9958. I had some ideas on how to build it, but i think that some 74xx are required for it. CPLD could be an option to reduce costs and chips.

One idea: replace DRAM chips used for VRAM with SRAM (similar as you did with ZX) and you will be able to control address lines ...

By RetroTechie

Paragon (1563)

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15-07-2010, 03:57

I had in mind to desing a character pattern generator for the V9938/V9958.
Care to elaborate what you mean?

One idea: replace DRAM chips used for VRAM with SRAM (similar as you did with ZX) and you will be able to control address lines ...
Wouldn't know for sure, but I don't think that's hard (likely in a similar way as with that ZX mod). No need for a CPLD there.

By RetroTechie

Paragon (1563)

RetroTechie's picture

18-07-2010, 11:12

Making some nice progress... Big smileBig smile I've implemented some of the logic you'd find in a memory mapper, and successfully tested that in hardware.

Yesterday I added some debouncing circuits to my test board. Read: circuitry that allows you to use manual switches to input clean, single 0 -> 1 and 1 -> 0 transitions to input clock/read/write pulses etc. That doesn't work with a simple on/off switch + pull-up resistor. And added some DIP switches to input more signals/data into the CPLD.

This morning I implemented 4 addressable registers (1 bit each for now), with read-back of those through the same pin (3-state I/O a la Z80 databus), and separate addressable output pin showing the internal bits. For the hardware builders among us: a 74HCT670 equivalent (but 1-bit wide), plus some surrounding circuitry. After some modifications, I tested this successfully in hardware too. Big smile (on my board that is, not as MSX peripheral).

It looks like the XC9536 is too small to put a full 4 MB mapper in it, need more I/O pins & internal resources for that. I'm not gonna buy new parts right now, but I think I'll be able to squeeze a 128~512K mapper into this part. Read: basically all logic you'd find inside a memory mapper, apart from DRAM control logic & memory chips.

If that works out, it would also mean that 1/2 Mbit ROM mappers could be done this way... 44-pin CPLD + 1 Mbit Flash ROM -> wire it up -> play! LOL!

By marlon-B

Expert (88)

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18-07-2010, 15:04

nice !

I never had to use cpld's .. cause of FPGA's

so it's interesting to follow your progress.

Do you have pictures of your setup ?

By RetroTechie

Paragon (1563)

RetroTechie's picture

18-07-2010, 18:30

I assume you missed the earlier thread ... (Bitcycle.org = my site)

I never had to use cpld's .. cause of FPGA's
You mean you used those? Building stuff with pre-programmed parts, or design too? :D

By marlon-B

Expert (88)

marlon-B's picture

18-07-2010, 23:55

no I mean because the first job I landed after school involved FPGA design for video surveillance systems.

and once you go FPGA you dont look back. You can virtually mimic any piece of electronics with it.

So never had the pleasure of using CPLD's professionally because it was not needed.

But now that I'm without a job at the moment I would like to look into it.

So very convenient that you're designing one right now.

Hope to learn alot while following your progress.

By RetroTechie

Paragon (1563)

RetroTechie's picture

23-07-2010, 02:49

Just finished a big round of testing on the first MSX hardware I put into a CPLD: a 64K memory mapper. Mapper consists of just 2 IC's (but looks like crap! Smile2): a 44-pin Xilinx XC9536 CPLD, and a 128K SRAM (70 ns) of which I'm using half. Didn't go for a bigger one because I considered it more important to test the function on different systems, than make something more complex, only to find out there's problems with it. SRAM hookup couldn't be simpler: #SLTSL -> #CS, #RD -> #OE, #WR -> #WE, with the CPLD controlling 2 of the higher address lines. Successfully ran some BASIC programs, a few games, and MAPTEST.COM (v4.2 by Maarten Verheijdt & Digital KC) with mapper stuck in below machines:

  • Philips VG 8020 (only verified mapper read-back & block switching on this machine).
  • Sony HB-F9P.
  • Sanyo Wavy 70FD2, at 3.58 and 8 Mhz.
  • 1chipMSX, at 3.58 and its turbo setting (10.7 MHz?)

So: small but fast. Big smile I've taken advantage of a nice feature of these CPLD's to initialize registers to known values at power-on. Read: when plugged into an MSX1, mapper blocks 3, 2, 1 & 0 are selected at power-on for pages 0~3, respectively. Should make MSX1+mapper combination a little easier. On MSX2 and above this makes no difference as the BIOS ROM sets these.

Uses ~50% of the CPLD's resources, should be a piece of cake to scale it up until this small CPLD is full (I'm guessing ~256K mapper should fit). Perhaps I'll publish some stuff once that's done. Next: put some DRAM control logic in that CPLD (a lot more tricky).

By RetroTechie

Paragon (1563)

RetroTechie's picture

28-07-2010, 18:22

Scaled up this mapper in the meanwhile: from 64 -> 128 -> 256 -> 512K (with a couple re-designs in between). What I have now works very well on all machines mentioned above (including 1chipMSX @turbo setting). Just some slight issues with mapper register read-back on the Sanyo Wavy FD2, but I think I know what the cause is. Mapper function itself feels rock-solid, no crashes or anything Smile (eg. played a few levels on my own R-Type crack, which needs 256K to work).

This fills the XC9536 completely. Perhaps I could squeeze in another step up (1M) if I'd drop the register read-back, but I don't think it's worth the trouble. A bigger mapper requires CPLD with more internal resources like XC9572(XL). Just for an idea: to implement same function using 74HC(T) logic, you'd need 6 IC's, plus all their interconnections. A single 12x12 mm IC is a lot more compact & easier to include in a PCB design.

Up next? dunno... time for a little break. Tongue

By RetroTechie

Paragon (1563)

RetroTechie's picture

03-08-2010, 18:51

Above issue on my Sanyo Wavy turned out to be a nasty problem, but another re-shuffling of CPLD contents fixed it. Latest iteration is reasonably compact, fast design & should be very robust timing-wise. Tested this version on all MSX machines I have (!), and found 0 errors no matter what speed or software I tried (R-Type crack on HB-75P MSX1... cool Cool ).

Still need to test on the popular 8250/55 machines, but I don't expect any surprises there. I think I'll publish this CPLD-based 512K mapper after I've had the chance to test on these Philips MSX2's (and perhaps Sony F700 or Turbo-R?).

By Latok

msx guru (3836)

Latok's picture

03-08-2010, 20:08

It's real nice reading your updates, Alwin. Thanks Smile

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