Hi,
I've build a JoyMega adatper into one of the very cheap and well known SMS pads from DX.com. I had some spare 74LSXX chips left over from another MSX related project, but no 7404 (well, actually that project is unfinished but I didn't feel like going to the store for <1€ parts, I can always get new ones). As a basis I was using the instructions from FRS's page.
EDIT: Forgot to mention, I've been using joytest 2.3b from FRS's page (utils section).
I used a HD74LS00P (quad NAND gate) at first. I though I need to short both inputs to get an inverter, but it didn't work as expected (I still don't know why, but I used pins 9-10, and 8 as output, and I presume it is possible that gate is broken).
Since that didn't work, Then I made another adapter with a SN74LS02J. I used another protoboard, an IC socket and some jumpers so I can test / troubleshoot with the NAND gate too :)
I presumed it should work without shorting the inputs. But, it didn't work as expected, either, but was detected as a 3-button SMS pad with left and right (!) both shorted (pressed) all the time. Using the pad does cause some reactions, but obviously it was not usable.
Then, I presumed I may have misunderstod something in the truth tables, so I tried to short both input (2&3). This way the pad works perfectly, all buttons! I believe was mixing (N)OR with X(N)OR logic. Only problem is, whenever I press up, "Z" button is also detected.
Then I tried the NAND gate again, this time with pins 1-3. Now it too works! It doesn't matter, wether I short pins 1&2 or not, which I find quite weird, but I believe I may have mixed up / misunderstood when the signal is low and when it is high in the circuit. So the chip may be broken (since pins 8-10 didn't work, but pins 1-3 work in otherwise identical circuit), or the other protoboard I'm using is broken somehow (I have double checked all solders, but I could always have made a mistake).
So, it seems that I'm using the logic gates the right way (please do correct me if I'm doing something wrong here!), but still something is wrong, since up causes Z to be detected ;) . This occurs with both logic gates. Any ideas what might be going on, or if I'm using the gates correctly? Or are they even usable this way?
Cheers!

).