TMS9929A Video Chip query

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By Tyune1

Rookie (18)

Tyune1's picture

21-09-2009, 14:58

Hi,

I am curious about how the VDP chip accesses video ram. the r/w output on pin 11 (active low) never seems to go low for writing to the VRAM, yet somehow the information gets through.

On my scope, there appears to be spikes instead of square wave, but connected to logic probe there is no change.

Is there anyone with knowledge of Electronics out there who could explain?

PS: I tried adding a logic gate to this pin and the output from that gate is showing up on the probe, but still a spike on the oscilloscope.

Thanks in advance!

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By RetroTechie

Paragon (1563)

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21-09-2009, 15:53

Under normal operation, a large part of the VRAM is read to construct a single screen - many times a second, continuously.

VRAM contents isn't changed much, or often. For example on a text screen, when you press a key, only 1 or 2 VRAM bytes need to be updated to show the corresponding character.

In other words: in normal operation, there are many, many, many reads (continuous) vs. very few writes (only when screen is changed). Since each single read or write is so short (microseconds at most), it appears as if there are only reads taking place, and (more or less) that reflects what's happening.

If you don't believe me: try hooking up a high speed, many-bit counter (say, 15 bits or more, a pair of 74HCT4040 in series, for example) to this R/#W signal. Each higher counter bit should toggle at half the frequency of the previous bit, so some high order counter bits will change slow enough that your eye can follow it. oO If the screen contents is changing, that is (so run a game, demo or something).

On my scope, there appears to be spikes instead of square wave
That's normal for logic signals! You only get a square ware with 50/50 duty cycle, fixed frequency signals (eg. a quartz oscillator clock output).

By PingPong

Prophet (4093)

PingPong's picture

21-09-2009, 19:34

Hi,

I am curious about how the VDP chip accesses video ram. the r/w output on pin 11 (active low) never seems to go low for writing to the VRAM, yet somehow the information gets through.

On my scope, there appears to be spikes instead of square wave, but connected to logic probe there is no change.

Is there anyone with knowledge of Electronics out there who could explain?

PS: I tried adding a logic gate to this pin and the output from that gate is showing up on the probe, but still a spike on the oscilloscope.

Thanks in advance!

On this forum less than one month ago i've opened a discussion about TMS VDP, with detailed tech info about the vdp itself.
The docs pointed out that for every scan line the vdp do 128 accesses in vram (a scan line is 64us), 8 are reserved for CPU access. So having the z80 writing data to VDP (a simple out(0x98),a) continously you should see a write every 8us, in active area.

In blank time the vdp is capable to make an access every 2us.

http://www.msx.org/forumtopicl10251.html

By Tyune1

Rookie (18)

Tyune1's picture

22-09-2009, 00:14

Thanks for replying,

The main problem I'm having is with regards to the 'duration' of the write strobe which connects to the VRAM itself, as opposed to how often the signals occur.

For example I applied the CSW signal to write to the chip (with mode input as 0 for VRAM writing).
I held it for say 1 second, however the r/w strobe is way shorter than that and is just a spike.
I first thought that the R/W strobe should be the same duration of the CSW strobe input but that doesn't appear to be the case.

According to the chip's datasheet the r/w should be active for around 190 nanoseconds. Could it be that the duration of the r/w strobe is taken direct from quartz clock?
Perhaps I will look at changing the value of capacitor surrounding the quartz, might be affecting the on/off ratio of the crystal.

your thoughts?

By MagicBox

Master (209)

MagicBox's picture

22-09-2009, 01:14

What's the bandwith of that logic probe and are you sure you don't have any capacitance in the probe line and have it grounded to the MSX / VDP GND?

To see square waves on a scope for the signal frequencies of the VDP you're going to need a good scope. 100Mhz would be sufficient to near properly display a 3.5MHz square wave.

By Tyune1

Rookie (18)

Tyune1's picture

22-09-2009, 10:02

both my logic probe and scope are 20Mhz. I have grounded with the vdp.

The odd thing is that I added an inverter gate at the output of the r/w and though my logic probe doesn't detect the r/w input to the gate, it does detect the output.
I'm thinking that the original signal may not be strong enough to be detected alone, and that by passing i through a logic gate, it is strengthened?
Possibly even the propagation delay in the logic is allowing it to show now?

By RetroTechie

Paragon (1563)

RetroTechie's picture

22-09-2009, 20:21

An oscilloscope is nice piece of kit, but mostly good to visualize low frequency, repeating signals / waveforms. Think analyzing audio amplifiers, filter circuits, power supply ripple voltages, that kind of thing. I get the feeling you're trying to use it as a logic analyzer - forget that, it won't work.

If you are: have you set the timebase to a suitable value (screen width = a few microseconds)? What are you using as a trigger signal? What voltage levels does the trigger input respond to?

Disclaimer: I don't have a scope myself, but know what it does and (roughly) how to use one - it's been a while though. Cool For repairs etc, I find a self-built logic tester a more useful / practical tool (and cheap too!)

By Tyune1

Rookie (18)

Tyune1's picture

24-09-2009, 11:26

Thanks for your reply guys.
Will certainly look into obtaining a logic analyser as it is something I have been trying to work around for a while, would be really usefull. I see a few homemade ideas on web, will give them a go.

Regarding the VDP, I have built a test circuit which doesnt seem to be working, it should be pretty simple and circuit as described below.

Firstly I have substituted the VRAM for a Flash ROM (70ns access) which I have pre-programmed with a VRAM memory dump from an active MSX emulator. I have setup the registers in the VRAM according to the emulator too which sets the base addresses, etc...

Regarding the electronics, the 8-address output from the VDP is connected to two 74LS373 latches which have the latch enables of each connected to the RAS and CAS outputs of the VDP.
The output of the latches follow the input, when the RAS is applied, the lower 8-bits of the address are latched to one of the 373's. then when CAS is brought low, the other 373 latch which provides the upper 6 bits of the address.
The output of these are fed into the ROM and the output of the rom is fed to the Read inputs of the VDP.

All I am getting on the screen are some vertical lines and cubes, they are stable so suggesting that there is something coming out of the ROM.
I have noted the labelling of the VDPs output lines (their msb bit is 0 whereas others are usually bit 7).
Cannot understand as everything appears to be connected and in theory it should work.

Any ideas why this may not work?
Thanks again Cool

By RetroTechie

Paragon (1563)

RetroTechie's picture

24-09-2009, 13:12

Yoy might want to replace, and re-wire those 74LS373 latches - take 374 or 574 type instead (1 should do), and an inverter. That latches the row address on the falling edge of #RAS, like a normal DRAM does. See my page here for details. Perhaps you could try with an SRAM first? And if that works, put your Flash ROM in place?

The VDP's data/address output lines are numbered, they need not necessarily match a programmer's view of the world / addressing scheme. And the relation VRAM address bit vs. DRAM address bit may change depending on screen mode. Not sure about MSX1 videochips on that one, but pretty sure that's true for the V9938 / V9958 chips. All a DRAM chip cares about is [row address] or [column address] and whether all rows are visited (=refreshed) within a maximum timeframe.

Also you're assuming an emulator's VRAM dump matches the physical memory of a real-world system. Now perhaps that would be nice, but what the hell for? An emulator's task is to duplicate behavior, not exact physical state. 16K RAM is just that, who cares whether it matches the contents of a DRAM connected to VDP chip? Compare swapping random address lines on an EPROM burner, burning an EPROM, and then swapping lines the same way on the circuit where you place the EPROM. The EPROM's contents seems scrambled, but a system programmer sees no difference. So your assumption of a 1:1 match there might be a bit optimistic.

Will certainly look into obtaining a logic analyser as it is something I have been trying to work around for a while, would be really usefull. I see a few homemade ideas on web, will give them a go.
What the hell would you need a logic analyzer for :-? I mean, that's some professional piece of hardware, and dozens of hardware builders have been fine building circuits for decades without one. Do you plan to invest the next 5 years of your live in a next-gen MSX model, or what? ;)

By Tyune1

Rookie (18)

Tyune1's picture

24-09-2009, 16:49


What the hell would you need a logic analyzer for Question I mean, that's some professional piece of hardware, and dozens of hardware builders have been fine building circuits for decades without one. Do you plan to invest the next 5 years of your live in a next-gen MSX model, or what? Wink

Yeah, silly isnt it, cant think where I got that idea from.
Still I think I will go with the logic tester as it would still be useful.

I did have the circuit with SRAM but that didnt work so decided to move onto the ROM with information already pre-programmed (that way eliminating the possibility that error is with writing to vram).
I needed two latches for the original SRAM, mainly due to the way that the VDP sends the info out of the AD0-AD7 lines in 3 separate stages (for example: lower address, then RAS..., higher address, then CAS..., VRAM data, then r/Write).

Are you saying that BluMSX emulator's 16K VRAM output is not the same what you would get if you examined the contents of a real MSX's 16K VRAM at the same stage? Why would the emulator's creator even bother with including that option?

By RetroTechie

Paragon (1563)

RetroTechie's picture

24-09-2009, 18:37

Are you saying that BluMSX emulator's 16K VRAM output is not the same what you would get if you examined the contents of a real MSX's 16K VRAM at the same stage? Why would the emulator's creator even bother with including that option?
No, I was saying you can't automatically assume it's layed out the same as the physical layout on real hardware. A better question is the reverse: why would an emulator creator bother to get this right? It's not every day that you move VRAM contents back and forth between real machines and emulators - it's more for snapshot purpose on the emulator itself. Perhaps you should ask BluMSX maintainers this?

You may be right on needing 2 latches tho - I missed that the TMS9929A (read: TMS9918) used it's VRAM address bus also to output VRAM data. And what's more: uses a different set of pins (RD0~7) to read back VRAM data (see "terminal assignments" ). And with LSB-MSB order reversed - nice WinkQuestion

There's a nice timing diagram in section 5-11 of the datasheet. Also see appendix B. Quote: "Valid data appearing on RD0-RD7 is strobed into the VDP when #CAS is brought high"

From the timing diagram I'd say you need to capture address data on falling edge of both #RAS and #CAS signal. That is: 373 logic type is no good, and for 374 or 574 type you need inverters between VDP signal and the latch's clock input. With that in place, I'd pick #CAS (non-inverted) as Chip Select for the Flash ROM, and ground it's Output Enable (or vice versa).

Other than that: some shuffling of address lines? If you get just 1 or 2 wrong, that may dramatically change the screen output. I think the TMS9929A is a more difficult chip in this respect than later cousins (V9938/V9958) with their 'flat' bitmap modes Crazy

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