VDP speed curiousity

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By sd_snatcher

Prophet (3499)

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18-12-2015, 21:08

Interesting! Do you know if the /INT pin is kept active after the VINT (or HINT) flag is lost?

By hit9918

Prophet (2921)

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19-12-2015, 07:06

I dont know.
I imagine the INT pin and the databus value are made by the same register bit.
maybe the INT pin bleeps for a short time.
but z80 doesnt look in that time.
the falling edge of z80 IO control line gotta clear the register.
between databus take and control lines falling, the interrupt generation makes the 1 and that event gets lost.
as short as that time is, shorter than a 5.4Mhz dot, it maybe is a rising edge. of a "line = 192" comparator. that needs no further "horizontal position = 0" comparator when its about that rising edge.

pure speculation Smile

By hit9918

Prophet (2921)

hit9918's picture

19-12-2015, 07:10

on the other hand I have the feeling that the overlap zone is bigger than those egdes who are like a tenth of a cycle.

By flyguille

Prophet (3028)

flyguille's picture

19-12-2015, 15:49

hit9918 wrote:

I dont know.
I imagine the INT pin and the databus value are made by the same register bit.
maybe the INT pin bleeps for a short time.
but z80 doesnt look in that time.
the falling edge of z80 IO control line gotta clear the register.
between databus take and control lines falling, the interrupt generation makes the 1 and that event gets lost.
as short as that time is, shorter than a 5.4Mhz dot, it maybe is a rising edge. of a "line = 192" comparator. that needs no further "horizontal position = 0" comparator when its about that rising edge.

pure speculation Smile

The z80 cpu clock is a subset of the vdp cpu clock, exist the possibility that when the z80 is reading the status register outside the ISR, it clears the INT status, before the z80 aknowledges that it has ben an interrupt. But it will depend on how the /INT of the z80 works, looks for the z80 manual in about how long must be the interrupt signal to be akanowledge.

Now, reading status register inside ISR can't be missed unless the z80 was delayed a whole vdp frame, aknowledge the first int but miss the second interrupt, for example interrupts overlapping.

By hit9918

Prophet (2921)

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19-12-2015, 17:16

I got to STRESS that there is no problem of "lost interrupts".
One looses the event in a polling loop of the status register.
With an interrupt handler, the IN 99 instruction happens "ages" after the INT pin went active.

The last code I posted goes with interrupt.
When the funny flicker is gone, then it was just that unrelated issue.

By flyguille

Prophet (3028)

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19-12-2015, 20:48

the other time, when upgrading to v9958, accidentally the /INT pin gets soldered together with the BLUE output signal.

The result, a bar was shown just in the next scan line below the Color/auto/goto/list/run patterns, that is the exactly point when /INT is activated, ISR routine can take one or one and half scan line to akanowledge, in that flicking way.

One, or One & half like as a switch flickering randomly.

By hit9918

Prophet (2921)

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19-12-2015, 22:46

wow! but the left side of the bar must have been always on the same pixel, no jitter.

By flyguille

Prophet (3028)

flyguille's picture

19-12-2015, 23:54

hit9918 wrote:

wow! but the left side of the bar must have been always on the same pixel, no jitter.

yes, it start in the same exact point always, but it is aknowledge by the isr in two moments differents, one scanline after, or one and half scanline after.

Other thing, I don't know if it is relevant, but remember that PAL/NTSC has interlaced scan lines, even frames, first scan line start (on the upper/left corner) and odd frames, first scan line start on the upper/middle of the screen, of the visible screen, or something like that... ofcourse VDP has borders, and it must have a timing mechanism to accomplish that standard.

By hit9918

Prophet (2921)

hit9918's picture

20-12-2015, 01:41

is that weird halve line off interrupt only in interlace mode.
there is a non-interlace mode, the normal thing for homecomputer,
every time send the same kind of frame, no interlacing, no flicker.
is there some 9938 special in that corner.

By Grauw

Ascended (10560)

Grauw's picture

20-12-2015, 02:15

If there’s a line delay (228 Z80 cycles per line), that’s due to the ISR handling overhead. All the push/popping the BIOS (or your own handler) does before your code can actuate the split I mean. If your split is done in H.KEYI, the BIOS ISR’s overhead is in that ballpark of 1-1.5 lines indeed.

Also the Z80 itself adds 14 or 19 cycles to jump to the ISR entry point, depending on the interrupt mode (IM 0-2). Additionally one must account for 0 to 25 more cycles due to instruction timing alignment, as the Z80 only responds to IRQs between instructions. That’s why a split that occurs mid-screen is not stable but oscillates (by up to 38 pixels).

Note also that some types of splits do not take effect immediately, e.g. setting the blanking only takes effect in the next hblank period (actually quite handy to make a tightly aligned blank line to cover up the splitting).

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