VDP speed curiousity

Some last results with the OTIR version. And another surprise:

1) I have a Sony HB-F1XDJ that I modded to connect the /WAIT pin of the V9958 to the Z80. When the WAIT is disabled, there are skipped frames just like the other MSX2+ models. When I enable the WAIT there are no more skipped frames at all. It can be clearly seem on the photo since the red will show up in a strong tone when the WAIT is enabled, while it's mixed with blue (or black, for the OUTI test) when the WAIT is disabled.

2) OneChipMSX hasn't skipped any frames either

Sony HB-F1XDJ_wait_disabled:

Sony HB-F1XDJ_wait_enabled:

One Chip MSX, HRA's with emsx_top_20080502_003 firmware at 3.57MHz

One Chip MSX, with HRA's emsx_top_20080502_003 firmware at 10MHz

The black zones are fully black. So this one no more is like the old issue when the test took more than one frame.
The red zones flicker? Every second frame the line interrupt status bit does not work?
I got no idea, I got no 9938, a question to emulator programmers

I am puzzled. Interrupt status bits that only work every second frame?
Did you make a stock boot, did you set interlace mode?

I wonder whether the whole flicker story is that 9938 too has a status register polling weakness. I thought it doesn't.
I wrote a version that uses an interrupt handler.
Now it slips more off the 0 line because of the bios overhead. Still one can nicely read things. Except the real machines come up with another voodoo to spoof it

10 clear 200,&hc000 : p% = &hc000 'loading asm there
20 defusr0 = p%
30 restore 10000 : gosub 5000 'load asm code

60 color 15,0,1 : screen 5 : set adjust(0,0)
62 open "grp:"as #1
65 for i = 0 to 211 step 8 : line (0,i)-(255,i),15 : preset(0,i) : ?#1,i : next
70 x=usr(0)

4999 STOP 'when above code forgot END
5000 read a$ : if a$ = "END" then return
5010 poke p%,val("&h"+a$) : p%=p%+1 : goto 5000


10000 DATA F3,CD,B8,C0,CD,33,C0,CD
10008 DATA 78,C0,3E,08,CD,5D,C0,1E
10016 DATA 0E,3E,01,CD,4F,C0,21,00
10024 DATA 64,ED,4B,06,00,0C,ED,69
10032 DATA ED,61,21,00,80,11,00,04
10040 DATA CD,85,C0,3E,00,CD,5D,C0
10048 DATA C3,07,C0,1E,13,3E,00,CD
10056 DATA 4F,C0,3E,01,1E,0F,CD,4F
10064 DATA C0,3A,DF,F3,CB,E7,32,DF
10072 DATA F3,1E,00,CD,4F,C0,C9,F3
10080 DATA ED,4B,06,00,0C,ED,79,7B
10088 DATA F6,80,ED,79,C9,F3,ED,4B
10096 DATA 06,00,0C,ED,79,3E,87,ED
10104 DATA 79,C9,F3,ED,4B,06,00,0C
10112 DATA ED,78,E6,01,C0,C3,6A,C0
10120 DATA FB,21,E9,C0,7E,E6,01,CA
10128 DATA 78,C0,36,00,C9,ED,4B,06
10136 DATA 00,14,1B,1C,7B,E6,F0,47
10144 DATA ED,A3,ED,A3,ED,A3,ED,A3
10152 DATA ED,A3,ED,A3,ED,A3,ED,A3
10160 DATA ED,A3,ED,A3,ED,A3,ED,A3
10168 DATA ED,A3,ED,A3,ED,A3,ED,A3
10176 DATA C2,90,C0,15,C2,90,C0,C9
10184 DATA F3,21,C5,C0,22,9B,FD,3E
10192 DATA C3,32,9A,FD,C9,3E,01,1E
10200 DATA 0F,CD,4F,C0,ED,4B,06,00
10208 DATA 0C,ED,78,32,E9,C0,3E,00
10216 DATA 1E,0F,CD,4F,C0,ED,4B,06
10224 DATA 00,0C,ED,78,32,E8,C0,C9
10232 DATA 00,00
10234 DATA END

        	org 0xc000 - 7
        	
        	db 0xFE
        	dw start
        	dw end - 1
        	dw start
		
start:  	di
		call patchint
		call setline
loop:   	
		call intsync
		
		ld a,8
		call color
		
		ld e,14
		ld a,1
		call setreg
        	
		ld hl,0x4000+72*128
		ld bc,(6)
		inc c
		out (c),l
		out (c),h
		
		ld hl,0x8000
		ld de,1024
		call copy
		
		ld a,0
		call color
		
		jp loop
	
RG0SAV equ 0xF3DF
RG1SAV equ 0xF3E0


setline:
		ld e,19		;interrupt line
		ld a,0
		call setreg

		ld a,1
		ld e,15
		call setreg 	;select s#1
		
		ld a,(RG0SAV)
        	set 4,a
        	ld (RG0SAV),a
        	ld e,0
        	call setreg
        	ret
		
		;vdp(e) = a
setreg:		di
		ld bc,(6)
		inc c
		out (c),a
		ld a,e
		or 128
		out (c),a
		ret
        	
        	
color:		di
		ld bc,(6)
		inc c
		out (c),a
		ld a,0x87
		out (c),a
		ret
        	
        	
sync:		di
		ld bc,(6)
		inc c

		in a,(c)
		and 0x01
		ret nz
		jp sync

intsync:	ei
		ld hl,s1
		ld a,(hl)
		and 0x01
		jp z,intsync
		ld (hl),0
		ret
        	
        	
copy:		ld bc,(6)
        	
		;de to format of nested jp nz
		inc d
		dec de
		inc e	
        	
		ld a,e
		and 0xF0	;align to 16
		ld b,a
cl:     	
		outi
		outi
		outi
		outi

		outi
		outi
		outi
		outi

		outi
		outi
		outi
		outi

		outi
		outi
		outi
		outi
		
		jp nz,cl
		dec d
		jp nz,cl
		ret
		
patchint:	di
		ld hl,int
		ld (0xfd9b),hl
		ld a,0xc3
		ld (0xfd9a),a
		ret
		
int:		ld a,1
		ld e,15
		call setreg 	;select s#1
		ld bc,(6)
		inc c
		in a,(c)
		ld (s1),a
		
		ld a,0
		ld e,15
		call setreg 	;select s#0
		ld bc,(6)
		inc c
		in a,(c)
		ld (s0),a
		ret

s0:		db 0
s1:		db 0
end:

when reading the status register in the same cycle as the VDP generates the event, the event is lost.
I thought it is only on MSX1, but the flicker stories here remind me of that issue.
better test with interrupt handler.
with an interrupt handler the cpu doesn't read the status register till the event happened.