Error compiling OCM source on Quartus II 9.1 SP1

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By Devcon

Resident (41)

Devcon's picture

10-02-2010, 17:50

Hello,

I have installed on Windows 7 x64, the Quartus II 64-Bit Version 9.1 1 Build 304 01/25/2010 SJ Full Version and the Service Pack 1.

I downloaded the latest stable sources from: http://webhome.look.ca/~aoboroc/08_06_15.zip

The target device selected for compilation is: EP2C20F484C7 (Altera DE1) and the Speed grade is 7.

I selected: Analysis & Synthesis Settings>VHDL Input>VHDL version>VHDL 1993.

I get 2 errors and 11 warnings when i start the compilation:

Error (10495): VHDL Subprogram Declaration error at vm2413.vhd(52): declaration of function or procedure "CONV_REGS_VECTOR" must have corresponding Subprogram Body
Error: Can't elaborate user hierarchy "eseopll:U32"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 11 warnings
Error: Peak virtual memory: 335 megabytes
Error: Processing ended: Wed Feb 10 17:47:28 2010
Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 11 warnings

Anyone can help to compile the sources?

Thanks in advance :)

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By lak

Rookie (21)

lak's picture

14-02-2010, 04:42

Hi,
I used quartus II 8.1 optimised for spped. It compiled successfully but with :

Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.

By Devcon

Resident (41)

Devcon's picture

14-02-2010, 12:58

For sythesizing a MSX i think the design don't need optimizations at all. The speed grade should be 7 as says the cyclone chip: F484C7, the last numer on the chip is the speed grade you should compile the code.

But i'm not 100% sure about it, if anyone that know more can explain what optimizations can be enabled on Compilation Process Settings would be great Smile

On a side note, i managed to compile the code on Quartus II 7.2 Web edition, but now i have 2 Quartus installed: 7.1 and 9.1, that sucks.
Still learning a little of VHDL so maybe in a future i will know to solve the compilation problem on 9.1 for myself. Maybe.

By Tanni

Hero (556)

Tanni's picture

15-02-2010, 14:16

Hello Devcon,

can you provide information on the compilation on Quartus II 7.2 edition? What VHDL version did you select there? Maybe you have to use other or additional libraries in version 9.1 to perform the same task.

By Devcon

Resident (41)

Devcon's picture

16-02-2010, 17:09

Hi Tanni,

Compilation settings are exactly the same on both versions, the VHDL version used is 1993 on both too. I think the problem is related to VHDL the code syntax, maybe they changed some standard behavior of the syntax on newer versions of Quartus or maybe they force the use of a more strict syntax, i don't know really what the problem is Question

About libraries i'm almost sure that the project use only IEEE external functions, so in both versions of Quartus should be installed by default.

By Tanni

Hero (556)

Tanni's picture

16-02-2010, 18:59

You can't change ''some standard behaviour of the syntax'', this is counterintuitive. Unfortunately, I don't know Quartus, we used Xilinx back in the day. But if there's a problem, it is most likely related to that you used the wrong librarys. Or you've forgot to include a library. You must do it directly before the declaration of an Entity. The scope of that declaration is only that Entity (and its Architectures).

Error (10495): VHDL Subprogram Declaration error at vm2413.vhd(52): declaration of function or procedure "CONV_REGS_VECTOR" must have corresponding Subprogram Body

You've declared a function or procedure CONV_REGS_VECTOR, but it requires you to also declare a subprogram which says what it means. As the code compiled in the 7.2 version, it must have gone lost in the 9.1 version.

BTW, what does that function or procedure do? If there's a REGS_VECTOR, which seems to be an register array, then CONV_REGS_VECTOR could be the driver function for it. We didn't cover that topic back then.

Can you provide some code snippets? Search the project files for some subprogram body of that CONV_REGS_VECTOR.

I don't know how much VHDL knowledge you have. Maybe more than I. If not, got to TNI, search for 'A taste of VHDL'. It is also available here on MRC. It just scratches the surface, but is better then nothing -- or better then being lost in a very large VHDL tutorial.

By Tanni

Hero (556)

Tanni's picture

16-02-2010, 19:04

About libraries i'm almost sure that the project use only IEEE external functions, so in both versions of Quartus should be installed by default.

Almost sure is not sure!

By Tanni

Hero (556)

Tanni's picture

16-02-2010, 19:33

If there's a REGS_VECTOR, which seems to be an register array, then CONV_REGS_VECTOR could be the driver function for it. We didn't cover that topic back then.
I meant resolution function.

But I've really no clue what CONV_REGS_VECTOR does.

BTW, as you installed and used a new version of Quartus, did you create a new project for your design in 9.1? Did you add all the necessary source files? If not, this could be the reason of that error. It compiled just the current source file, but didn't include the other files of that design.

Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:03

This would explain the low elapsed time and total CPU time, too.

Sometimes, if nothing works anymore, it's maybe because the project is corrupted. Then you need to make a new project in a new project directory, copy all the source files there, add them to the project, and there you go.

Strange and unpredictable things happen, alas!

Now, my train is gone and I've to wait one hour for the next one.

By Edwin

Paragon (1182)

Edwin's picture

16-02-2010, 19:51

Devcon> The file in question is a fairly standard package file. I see the declaration you named at line 55, not 52, so it may be worthwhile to check whether your source isn't damaged. Anyway, the function is implemented starting on line 302 in the package body section.

By Tanni

Hero (556)

Tanni's picture

16-02-2010, 19:56

A taste of VHDL . . . at

www.msx.org/forumtopic6502.html

Whow, just discovered that it is forum topic 6502!

map.grauw.nl/articles/taste_of_vhdl.php

Thanks Grauw for rendering it in such a nice way!

By Devcon

Resident (41)

Devcon's picture

17-02-2010, 04:14

I'm just learning and i'm still a noob, my knowloedge of VHDL is maybe a 2% hehe Smile

I downloaded the source from a dhau post here: http://webhome.look.ca/~aoboroc/08_06_15.zip

I made a clean and full installation of Quartus II 9.1, next i open the main project file: emsx_top.qpf, i verified the settings are correct: speed grade 7 & unused pins as input tryi-stated, nothing more.

I don't have changed a single line of code, but when i start compilation i get the errors:

Error (10495): VHDL Subprogram Declaration error at vm2413.vhd(52): declaration of function or procedure "CONV_REGS_VECTOR" must have corresponding Subprogram Body
Error: Can't elaborate user hierarchy "eseopll:U32"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 11 warnings
Error: Peak virtual memory: 338 megabytes
Error: Processing ended: Wed Feb 17 04:08:32 2010
Error: Elapsed time: 00:00:09
Error: Total CPU time (on all processors): 00:00:05
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 11 warnings

Nothing less, nothing more.

I don't coded that, my knowloedge for that is very low, but i like to compile the design then i can see in the RTL viewer the 'schematics' of the circuit just for learning.

Maybe is a library problem, i don't know. I just want to know if anyone have compiled that source on the latest version of Quartus sucesfully :)

Regards.

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