One chip MSX improvement project

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By DarkSchneider

Paladin (906)

DarkSchneider's picture

06-12-2019, 15:09

HRA! wrote:

As for the scale of FPGA, I think there is capacity to implement R800.
I think that the same access as R800 is difficult because of SDRAM access problem.

Even though SDRAM has a lot of command overhead, it is structured to be accessed from both the CPU and VDP at about 4x speed.
The only idea is to create a new FPGA board with separate CPU SDRAM and VDP SDRAM, or clock up more.
In order to manage with the current device, it is necessary to raise the clock, but the current double speed exceeds the SDRAM specification.
I want to carefully consider how to respond.

So tha main problem if I understood right would be at that using the same SDRAM pool and cannot set different waits for CPU and VDP accesses.

By HRA!

Master (213)

HRA!'s picture

06-12-2019, 15:10

lintweaker wrote:
erpirao wrote:

would it be possible to use y80e or nextz80 cores for the r800?
nextz80
y80e

These are both written in Verilog while the current T80 and the rest of OCM is written in VHDL. Mixing them is (should) be possible but I think it makes things more difficult.

All the circuits recently added to emsxcv are written in Verilog (tr_pcm.v, s1990.v etc...).
So mixing Verilog and VHDL is not a problem.

However, since I want to crush the problems one by one, I would like to try to solve the problem of using the turboR BIOS rather than replacing the core.

By HRA!

Master (213)

HRA!'s picture

06-12-2019, 15:15

DarkSchneider wrote:

So tha main problem if I understood right would be at that using the same SDRAM pool and cannot set different waits for CPU and VDP accesses.

That's right.
That is the biggest problem.

Real MSX uses different DRAM for CPU and VDP. CPU and VDP can be accessed at any time.
However, OCM shares with CPU and VDP. If one timing changes, the other timing is affected. Crying

By HRA!

Master (213)

HRA!'s picture

08-12-2019, 21:53

By HRA!

Master (213)

HRA!'s picture

09-12-2019, 15:20

OCM has a bug that sprite attribute table address update has delay.
I created a test program for verification.

http://hraroom.s602.xrea.com/ocm/files/ocm_test_for_ToDoList...

Use this to consider how to fix it.

By Parn

Hero (516)

Parn's picture

09-12-2019, 15:28

HRA! wrote:

I have created ToDoList.

Thank you, it's very appreciated.

By HRA!

Master (213)

HRA!'s picture

21-12-2019, 23:14

I have updated ToDoLists.
http://hraroom.s602.xrea.com/ocm/files/ToDoLists.pdf

Item#1: Sprite delay bug is very hard. I am trying to improve it by redesigning vdp_sprite.

By HRA!

Master (213)

HRA!'s picture

04-01-2020, 10:39

Happy new year! ;-)

https://twitter.com/thara1129/status/1213217794759675905?s=19

I am in the process of recreating vdp_sprite.
The purpose is to improve the processing timing of sprite. It will take a little longer to complete the work.
:)

By hamlet

Scribe (3043)

hamlet's picture

04-01-2020, 10:45

Whoooo! Nice progress!

By HRA!

Master (213)

HRA!'s picture

04-01-2020, 13:28

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