Hey CARO, what are the keyboard shortcuts to switch between SCC, ASCII8 and ASCII16 cartidges?Not yet.
We need to be done
ok! Using the switches for now then. Thanks!
BTW: have you ported other platforms to Altera DE1? There are Atari ST, C64 and Amstrad CPC cores with source code available, too.
The CPC core was working on the old Altera C1 board. Have you looked at these sources?
The link for latest stable release OCM on Altera DE1speccy.ifolder.ru/13159085
Hi caro,
I hate to keep bothering you, but the new link also doesn't work for me. The page is there, but no download option is offered. It is funny that if I use Google to translate the page, then a download option is displayed (two radio buttons and a text that a must enter). I have no idea what the problem is, but anyway, I would love to download the last stable version because I just got a DE1.
Thanks again!
ifolder.ru requires you to watch some adds if you're from outside of Russia, and it's all explained in cyrillic. I downloaded the archive and uploaded it to my homepage @ ISP. Enjoy: 08_06_15.zip
dhau,
Thank you so much!!
Please download from my mirror now, because it'll probably be gone after mid-September.
I've canceled my DSL and land line due to Bell Canada going into suicidal anti-customer mode. Guess what? Even in my back water US appendage country customers have some choice.
I have been thinking about it for weeks now: If the VDP9958 is an evolution over the VDP9918 in the first MSX, and the Master System VDP is derived from the 9918... how compatible is the 9958 with the master system VDP??
Shouldn't be possible to add Master System VDP support to the OCM core and load Master System games??
I'm trying to understand (from my very low level of VHDL experience) if (and how) ocm performances could be improved.
In particular I'm focused on sdram controller/arbitrer.
If I understand correctly:
1) sdram actually works @ 85MHz with a CAS latency = 2.
2) sdram datasheet reports max working frequency = 160MHz but CAS latency needs to be become 3.
3) ram/vram access bandwidth is limited to an effective 10,5MHz because sdram controller circuitry is based upon an 8 states statemachine, this implies limiting core frequency to 10,5MHz
Now here are my questions:
1) clocking T80 @ 21MHz has proven to provoke instability, did anybody try with an intermediate 14MHz 
2) apart from optimizing T80 execution timing, is there a way to improve ram access bandwidth (and so cpu performance) by using an higher sdram frequency still mantaining stability 
Thanks for your attention
When I was changing the memory controller, I analysed the code and came to the conclusion that it's desperately needs replacement. It doesn't process actual requests at all, it just reads ram or vram address on the bus based on whether the vdp clock is even or odd.
The 21 MHz may not directly be a problem since none of the chips can do memory access on every clock.
But I do think that memory bandwidth could be increased a lot if a good memory controller was written.
HRA! and KdL,
I do have a feature request to improve the OCM. Could you please try to implement the support for the NUMLOCK key? This would workaround the annoying LEFT+UP+SPACE bug that many PC keyboards have, because this bug don't happen when the numeric pad arrows are used.
The NUMLOCK should work as expected: When turned on (default) it will send numbers to the MSX. Then turned off, the numeric pad behaves as arrows + HOME etc.
I know the NUMLOCK key currently produces the "," of the MSX numeric pad, but this comma could be easily relocated to another free key, like ScrollLock or END. Or even better, ScrollLock itself could be used to behave as the NumLock feature.
What do you think about it? It it too hard to implement?
