What is Next ??

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By erikmaas

Resident (63)

erikmaas's picture

09-09-2005, 17:02

@Leo: I guess that you took care to put the memory busses and video output to the pins of the spartan? This is very important, otherwise a large part of your design will be optimized away depending on the quality of the optimization... But still that does not explain this large difference, considering that you probably had the same top-level design for both devices.

@Pat: The lab name used to be PDSL indeed.

By Leo

Paragon (1236)

Leo's picture

09-09-2005, 18:47

Yes I realize i was not clear.
Indeed I did a first synthesis with a wrong spartan version as target fpga and got around 35MHz.
Each time i re-run the synthesis this value varies a little, 1MHz at most.
When setting the right spartan (xc3s1000) device the frequency got much higher.
But the design has not the definitive constraints : pin positions , external clock to sdram...
An other problem is a warning that says that my frequency generated by the DCM blocks is too low :
21Mhz while minimum is 24MHz, but it is just a warning ...
An other surprise is the number of flip flops , 1000 for VDP ,only 300 for Z80, I would have said the
contrary...

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