V9990 write mask

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Par PingPong

Prophet (3501)

Portrait de PingPong

25-12-2019, 11:15

Hi all, and best wishes.
I' ve read about V9990 write mask but it is unclear to me how this work.
V9990 has no logical block operations. Do I need to set this register when performing pixel related block move?
For example with a mode that stores two pixels in a byte what is the value of the write mask when addressing single pixels?
It is required to use it?

And finally write mask interfere with the byte written to like it does the transparent bit.
What is the order however? First logic operation then write mask or vice versa?

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Par Manel46

Hero (517)

Portrait de Manel46

25-12-2019, 12:00

I do not understand this well. But from experience write #FF for P1 and #FFFF for Bx modes.
This at the beginning, at the start of the program. Just one time.
Merry Christmas!

Par PingPong

Prophet (3501)

Portrait de PingPong

25-12-2019, 21:20

Merry Christmas to you too. But it is unclear why two values. Anyone knows?

Par PingPong

Prophet (3501)

Portrait de PingPong

26-12-2019, 18:12

So insn't there a better explanation on how V9990 write mask work?
assuming that the emulation code taken from openmsx source is correct it does appear to me that a different byte is used for the mask based on the vram address used... but this is unclear why...

inline void V9990CmdEngine::V9990P1::psetColor(
         V9990VRAM& vram, unsigned x, unsigned y, unsigned pitch,
         word color, word mask, const byte* lut, byte /*op*/)
 {
         unsigned addr = addressOf(x, y, pitch);
         byte srcColor = (addr & 0x40000) ? (color >> 8) : (color & 0xFF);
         byte dstColor = vram.readVRAMDirect(addr);
         byte newColor = logOp(lut, srcColor, dstColor);

         byte mask1 = (addr & 0x40000) ? (mask >> 8) : (mask & 0xFF);
         byte mask2 = mask1 & (0xF0 >> (4 * (x & 1)));
         byte result = (dstColor & ~mask2) | (newColor & mask2);

         vram.writeVRAMDirect(addr, result);
 }

Par Juan Luis

Expert (100)

Portrait de Juan Luis

26-12-2019, 20:44

Yamaha VDP V9990 manages memory with two memory channels. It's a dual channel VDP. If you take a look on Yamaha V9990 manual page 4, you will be able to see V0A0 - V0A8, V0S0-V0-S7 addresses pins and V0D0-V0D7 data pins for first memory bank and V1A0-V1A8,V1S0-V1S7 addresses pins and V1D0-V1D7 data pins for second memory bank. Yamaha VDP can access to first and second bank with different addresses for each channel at same time. This is done for making quicker memory transfer in P1 mode. In P1 mode, V9990 has to access to memory in order to get the information of Plane A (front parallax plane) and Plane B (background parallax plane). Plane A patterns are stored in first bank (lower addresses bank) in range 00000-3FFFF, and Plane B patterns are stored in second bank (high addresses bank) in range 40000-7FFFF.

BD16 mode (16 bits per pixel) stores the information of each pixel using two bytes. First byte is stored in lower memory bank and second one is stored in higher memory bank. V9990 sends same address to both memory banks to get both bytes. The cost of accessing to pixel information in BD16 mode is equal to BD8 thanks to both memory channels.

Registers #46 and #47 Window Mask (low and high) are used to select banks. V9990 commands are also available in P1 mode, but the V9990 command engine was designed for bitmaps mode working in both banks. In order to use command engine in P1 mode you have to use window mask to select the bank where the operation is executed. For instance, if you want to execute a PSET command in P1 mode Plane A Pattern Definition Table you have to set Window Mask to 0x00FF and if you want to do same thing in Plane B Pattern Definition Table you will have to set Window Mask to 0xFF00. Drawing in P1 mode is like drawing in B1 mode 256 pixels width of image space with BP4 pixels (4 bits/pixels with palette).

Par PingPong

Prophet (3501)

Portrait de PingPong

26-12-2019, 22:24

Thanks for explanations. I need to think about your description to understand more in detail but it does appear that write mask take effect after selecting the logical nibble where the pset is applied in a 4 bit / pixel mode and after taking in account the transparent pixel function.
But I have a suspect that doing a block move between plane a and plane b is not possible. Or I am wrong?

Par Juan Luis

Expert (100)

Portrait de Juan Luis

28-12-2019, 11:46

Sorry for my delay answering your question. I'm not sure about your last question.

I have done several tests and the execution of BMXL, BMLX and BMLL were unsuccessfully in P1 mode with many different Window Mask combinations. I'm a little bit surprised because I thought these commands worked fine in P1 mode, but I couldn't transfer data properly even between areas of same plane Question . So, this breaks my ideas.

However, I was able to execute LINE command on PGT A (in OpenMSX) and I was able to see the line on screen. I had to write on PNT A a sequence of name pattern starting from zero in order to see the content of PGT A.

Sorry PingPong. I wasn't very helpful.
I'll continue doing tests.

Please, if someone has more information about this topic, help us.

Thanks, in advance.

Par PingPong

Prophet (3501)

Portrait de PingPong

28-12-2019, 12:04

you do not need to apologize.
Unfortunately the lack of real hw make difficult to understand how this thing work.

Anyway i think it should be very interesting to know the details, actually the v9990 is getting more interest.
So, if you discover other things do not esitate to share!

More, maybe a thread should be opened on this topic allowing others that experiencied with v9990 to contribute!

Par PingPong

Prophet (3501)

Portrait de PingPong

28-12-2019, 14:42

I think GhostWriterP had done come experiments in P1 mode with BMLx commands initially reporting they not worked as expected but finally saying it was a problem related to him not the V9990, and that the V9990 worked well.
Maybe can shed some light about P1 & V9990 engine

Par hit9918

Prophet (2886)

Portrait de hit9918

28-12-2019, 19:34

maybe the blitter works the same in all modi? then one can guess what the byte commands do in P1 mode.
why does the blitter hit layer A and layer B at the same time. this very much smells like the blitter does a 16bit acess. with the 2 address buses showing the same address.
maybe the blitter goes the same as in 16bit per pixel mode.

most people get first contact with the mask register in P1 mode as "enable in layer A, enable in layer B". making it kinda an address thing.
but it does enable things BIT WISE, doesnt it? this is about a whole new set of fx beyond MSX2!

it can select the R in 16bits of RGB.
it can select 1 bit in paletted mode to blit some amiga agony moon as third layer!!

Par hit9918

Prophet (2886)

Portrait de hit9918

28-12-2019, 21:19

from some other thread I got the idea that the blitter does blit in layer A and layer B at the same time. and that one usualy does disable one with the mask registers.
but in the manual is said that in P1 mode the bits SX9 and DX9 select layer A vs layer B.

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