Ninja tap

Paladin (1007)

07-07-2009, 17:27

Hello all,

i am looking for information about Ninja Tap device.
As far as i know, this device allowed to connect up to 4 joysticks in one port to play some special games.
Only game i know that used this was Magical Labyrinth.

I would like to know technical details about it, such as internal schematics (if possible), how namy and wich games were made for it.

I am thinking of a proyect and I would like to build one by myself.

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Par Manuel

Ascended (19471)

07-07-2009, 23:45

You could check out the source code of openMSX to see how it's implemented there.

Par Danjovic

Champion (336)

13-09-2022, 06:42

This is a 13 year bump but here we go!

I tried to look at the code of openMSX but couldn't figure out the behavior of the device.
Then I got the code of DM system 2 and found something odd at the CHECK routine.
The output ports are all lowered down, then the state of pin 7 is tested.
If pin 7 is LOW then the function return as if there is no Ninja tap at the port, otherwise the code flips the state o pin 8 and check again the state of pin 7. This time it expects the pin to be low. In other words pin 7 must be receive the opposite state of pin 8.
But there's a catch. Pin 7 is an open collector, and something on the Ninja Tap will need to force a HIGH level on the pin that is being driven LOW. It does not look good to me.

Anybody else have wondered about that?

;======================================
; Connection Check Sub.
; return with B=B+1 if no hardware detected
; otherwise return with B=B+4 if hardwar detected
CHECK:	CALL	PORSEL   ; 
	INC	B          ; B = Max player number + 1
	AND	0C0H       ; A is state of port 15. 
	OUT	(0A1H),A	; 678=L  for both joystick ports (!)
	EX	AF,AF'      ; save state of Reg15 with all output pins low
	
	LD	A,14        ; select register 14 
	OUT	(0A0H),A
	IN	A,(0A2H)    ; read state of joystick port
	AND	20H		    ; 7=H ?   return if bit is high (!) (shouldn't be forced high, its being driven low internally )
	RET	Z           ; if return here, A = state of pin 6, and B=B+1 from the function call
	
	LD	A,15        ; select register 15
	OUT	(0A0H),A
	
	EX	AF,AF'      ; restore state of Reg15 with all output pins low
	OR	030H        ; make bits 4 and 5 high (pin 8 of both pulse pins)
	OUT	(0A1H),A	; 8=H  for both output ports
	
	LD	A,14        ; select register 14
	OUT	(0A0H),A
	IN	A,(0A2H)    ; read inputs  
	
	AND	20H		    ; 7=L ? is pin 7 low
	JR	NZ,CHECK1   ; no, return with A=0

	INC	A           ; Complement bit 0 of register A (read from pin 6) 
	INC	B           ; B = B+3
	INC	B
	INC	B
	RET
; No NTAP
CHECK1:	XOR	A
	RET

Par gdx

Enlighted (6223)

13-09-2022, 10:00

People who own a Nijatap should not be numerous. Have you tested it on OpenMSX?

If it works, we could put it on the wiki page.
https://www.msx.org/wiki/PCCM_Ninja_Tap

Par Danjovic

Champion (336)

13-09-2022, 16:00

I am trying to figure out the schematics of the Ninja Tap by analyzing the assembly code.

Par Danjovic

Champion (336)

14-09-2022, 06:48

So far, the Ninja Tap uses four CD4021s to shift out the data from the 4 controllers.
Pin 6 goes to PARALLEL/!SERIAL of the 4021s
Pin 8 goes to CLOCK of the 4021s
Pin 7 receives the inverted level of signal from pin 8 (!)
Pin 1 receive the data out from the first tap port
Pin 2 receive the data out from the second tap port
Pin 3 receive the data out from the third tap port
Pin 4 receive the data out from the fourth tap port
Pin 5 is the VCC
Pin 9 is the GND

disassembling the GETNIN function :

The sequence for reading the 4021s is the following
0) the sampling start with pin 8 (CLOCK = HIGH) and pin 6 (PARALLEL/!SERIAL = LOW)

1) pulse (go high, then low) the PARALLEL/!SERIAL line (pin 6). That will latch the input of the keys to the 4021 internal flip flops. Notice that the CD4021 output is already loaded at the Q8 output.
2) Pulse (go high, then go low) the CLOCK line (pin 8). (note: If this pin weren't initialized high, the first bit would be missed)
3) shift in one data bit from TAP 1 at the UP line (pin1) into register H
4) shift in one data bit from TAP 2 at the DOWN line (pin2) into register E
5) shift in one data bit from TAP 3 at the LEFT line (pin3) into register D
6) shift in one data bit from TAP 4 at the RIGHT line (pin4) into register C
7) Repeat steps 2 through 6 for seven more bits

Waveform:

The sequence of bits is the same used by NES controllers, being possible to make an adapter that uses 4 NES controllers with only one inverter.
I can think of way of wirign a Joymega to create a Ninja Tap with NES clone controllers, lol!

More details on Detection quirk:
Pin 7 is an open collector and the detection routine pulls this pin down (instead of let it float ) during the detection, which means that the external inverter will have to fight (and win) against the internal 7407 open collector gate, otherwise the detection will fail.

Par Danjovic

Champion (336)

15-09-2022, 03:08

I could not find the source code for the NinjaTap, as mentioned in this reference, but I believe part of the original code remains on the DM System source code. If that is true, the original driver did not held down pin 7.

; Port1 ID Check
;	LD	 H,0FFH
;	RRCA
;	LD	DE,0BA3AH     ; -> D = mask for cleaered bits, E mask for set bits
;	CALL	 C,GETID  ; Call Check ID with masks defined so pin 7,8 high, and pin 6 low
;	RRCA
;	LD	A,H
;	LD	(RESULT+2),A
; Port2 ID Check
;	LD	H,0FFH
;	LD	DE,0FA7AH
;	CALL	 C,GETID
;	LD	A,H
;	LD	(RESULT+3),A
; Restore Port (6,7,8=H)
	LD	DE,0FF3FH   ; 678=h on both ports
	JP	PORSEL
;	EI
;	RET

And it looks like the ID was check differently, reading the state of the 9th input (SI) of the 4021s

;======================================
; Get ID
;GETID:	PUSH	AF
; 6=H 8=H          ;-> Indeed 6=L when this function is called
;	CALL	PORSEL        
; 6=H 4021 Data Load
;	OR	05H      ; -> now set (or make sure that) pin  6 is high      
;	OUT	(0A1H),A
; 6=L 4021 Transfer Mode
;	AND	0FAH             ; bring pin 6 low
;	OUT	(0A1H),A
;
;	LD	B,9
;/// Waste 8 Data and Get 9th Data ////
;GETID0:	LD	A,15
;	OUT	(0A0H),A
;	IN	A,(0A2H)
; 8=H
;	OR	30H
;	OUT	(0A1H),A
; 8=L (Send me Data)
;	AND	0CFH
;	OUT	(0A1H),A
; Data Read
;	LD	A,14
;	OUT	(0A0H),A
;	IN	A,(0A2H)
;	DJNZ	GETID0
;////////////////////////////////////
;	AND	0FH   -> ID should be set on the 9th input bit of the 4021s from NinjaTap
;	LD	H,A
; Restore Port (6,7,8=H)
;	LD	A,15
;	OUT	(0A0H),A
;	IN	A,(0A2H)
;	OR	03FH
;	OUT	(0A1H),A
;
;	POP	AF
;	RET
;======================================
; Sub Routine

Par Danjovic

Champion (336)

15-09-2022, 03:57

By the way I have drawn an schematic of what could be the Ninja Tap adapter. Notice the inverter implemented with a transistor to avoid signal contention (conflict) if pin 7 is held down while pin 8 flips.