memory expansion using SRAM ( 512K*8bit chips), many alternatives?

By popolon_

Champion (321)

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27-06-2020, 13:10

It started when I noticed that the there is memory upgrade for yamaha yis-503III
http://caro.su/msx/mem4msx.htm
and then noticed that I need to add missing ICs to my YIS-503II, IC312 (74LS32), IC319 (74LS30) ja IC315 (74LS04) ) so it would work.
But then I find out other 512Kb SRAM project based on CPLD Xilinx XC9536-7C-VQ44:
https://www.circuitsonline.net/forum/file/45018
And that is different, signals used from MSX are not exactly same. But SRAM chips are compatible ( K6X4008C1F-BF55 vs BS62LV4006PIP55)

YIS design uses YIS pin signals AB0-AB1,A2-A14,D0-D7,WE,CAS2,MAPRD,MAPWR but original signals are :
AB0-AB1,AB2-AB7,
A2-A14,
D0-D7,
WE,
CAS2,
MI-B,
IORQ-B when taking into account the IC312,IC315,IC319 in yamaha side.

512K SRAM CPLD project uses slot signals:
AB0-AB14
DB0-DB7
IORQ-B
BUSDIR
SLTSL -> #ChipEnable
RD-B -> #OutputEnable
WR-B -> #WriteEnable

So how are these designs so different implementation? As for example OE pin is connected to CAS2 in YIS design, but it is connected to slot RD pin in that 512K design. And WriteEnable pin is connected to WE signal in YIS design, but into WR-b in 512K design. And ChipEnable pin is connected to own logics in YIS design, but into slot SLTSL pin in 512K design. And BUSDIR is used in only 512K design.

And why there is sometimes address lines AB0/AB1 or A0/A1? Is there difference which kind of is connected? ROM chips are receiving the address lines A0-A15, and slot connector always AB0-AB15, but for memory mapper connection, is there a difference which one to use? And same for datalines D0-D7/DB0-DB7, is there a difference?

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