Need help translating Japanese to English

ページ 2/2
1 |

By dhau

Paragon (1570)

dhau さんの画像

13-06-2008, 23:31

Mkay, I'll try to make more sence from schematics above, even if I'm not really qualified.

Z80/S1985 outputs:

~RD - when low, cpu gets value from from data bus (D0-D7, could be memory or i/o)
~WR - when low, cpu puts value on data bus
~RFSH - when low, A0-A6 has DRAM address to be refreshed
~MREQ - when low, ~WR/~RD work with DRAM, when high, with i/o
~BUSACK - if low, external device can start using data/address buses after it requested them through ~BUSRQ
~SLT3X - if low, X sub-slot of 3-rd slot is selected

Self-refreshing DRAM inputs:

~WE - if low, read value from data bus to address from address bus
~CE - if low, enable chip
~OE/~RFSH - (need more research) if low, put DRAM data to data bus from address on address bus (and probably refresh row if Z80 ~RFSH is low)

OR output is high, if either of inputs is high
NOR output is only high, if both inputs are low

Meaning (hopefully):

~WE=~WR
Straight forward, cpu puts data on bus, DRAM reads it

~CE=~SLT3X OR (~BUSACK NOR 0)=~SLT3X OR (NOT ~BUSACK)
Only enable DRAM if S1985 is selecting right subslot and Z80 holds the buses

~OE/~RFSH=((~SLT3X NOR ~RD) OR (~RFSH NOR ~MREQ)) NOR ~BUSACK

~SLT3X	~RD	~RFSH	~MREQ	~BUSACK	~OE/~RFSH
-------------------------------------------------
0	0	0	0	0	0	((0 NOR 0) OR (0 NOR 0)) NOR 0=(1 OR 1) NOR 0=1 NOR 0=0
0	0	0	0	1	0	((0 NOR 0) OR (0 NOR 0)) NOR 1=(1 OR 1) NOR 1=1 NOR 1=0
0	0	0	1	0	0	((0 NOR 0) OR (0 NOR 1)) NOR 0=(1 OR 0) NOR 0=1 NOR 0=0
0	0	0	1	1	0	((0 NOR 0) OR (0 NOR 1)) NOR 1=(1 OR 0) NOR 1=1 NOR 1=0
0	0	1	0	0	0	((0 NOR 0) OR (1 NOR 0)) NOR 0=(1 OR 0) NOR 0=1 NOR 0=0
0	0	1	0	1	0	((0 NOR 0) OR (1 NOR 0)) NOR 1=(1 OR 0) NOR 1=1 NOR 1=0
0	0	1	1	0	0	((0 NOR 0) OR (1 NOR 1)) NOR 0=(1 OR 0) NOR 0=1 NOR 0=0
0	0	1	1	1	0	((0 NOR 0) OR (1 NOR 1)) NOR 1=(1 OR 0) NOR 1=1 NOR 1=0
0	1	0	0	0	0	((0 NOR 1) OR (0 NOR 0)) NOR 0=(0 OR 1) NOR 0=1 NOR 0=0
0	1	0	0	1	0	((0 NOR 1) OR (0 NOR 0)) NOR 1=(0 OR 1) NOR 1=1 NOR 1=0
0	1	0	1	0	1	((0 NOR 1) OR (0 NOR 1)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
0	1	0	1	1	0	((0 NOR 1) OR (0 NOR 1)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
0	1	1	0	0	1	((0 NOR 1) OR (1 NOR 0)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
0	1	1	0	1	0	((0 NOR 1) OR (1 NOR 0)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
0	1	1	1	0	1	((0 NOR 1) OR (1 NOR 1)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
0	1	1	1	1	0	((0 NOR 1) OR (1 NOR 1)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
1	0	0	0	0	0	((1 NOR 0) OR (0 NOR 0)) NOR 0=(0 OR 1) NOR 0=1 NOR 0=0
1	0	0	0	1	0	((1 NOR 0) OR (0 NOR 0)) NOR 1=(0 OR 1) NOR 1=1 NOR 1=0
1	0	0	1	0	1	((1 NOR 0) OR (0 NOR 1)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
1	0	0	1	1	0	((1 NOR 0) OR (0 NOR 1)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
1	0	1	0	0	1	((1 NOR 0) OR (1 NOR 0)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
1	0	1	0	1	0	((1 NOR 0) OR (1 NOR 0)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
1	0	1	1	0	1	((1 NOR 0) OR (1 NOR 1)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
1	0	1	1	1	0	((1 NOR 0) OR (1 NOR 1)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
1	1	0	0	0	0	((1 NOR 1) OR (0 NOR 0)) NOR 0=(0 OR 1) NOR 0=1 NOR 0=0
1	1	0	0	1	0	((1 NOR 1) OR (0 NOR 0)) NOR 1=(0 OR 1) NOR 1=1 NOR 1=0
1	1	0	1	0	1	((1 NOR 1) OR (0 NOR 1)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
1	1	0	1	1	0	((1 NOR 1) OR (0 NOR 1)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
1	1	1	0	0	1	((1 NOR 1) OR (1 NOR 0)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
1	1	1	0	1	0	((1 NOR 1) OR (1 NOR 0)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0
1	1	1	1	0	1	((1 NOR 1) OR (1 NOR 1)) NOR 0=(0 OR 0) NOR 0=0 NOR 0=1
1	1	1	1	1	0	((1 NOR 1) OR (1 NOR 1)) NOR 1=(0 OR 0) NOR 1=0 NOR 1=0

So, ~OE/~RFRH is always disabled if external device uses the buses (~BUSACK is low). Also it's disabled if cpu isn't trying to read (~RD) from proper slot (~SLT3X), or if CPU isn't refreshing DRAM (i.e. either ~RFSH or ~MREQ aren't active).

~SLT3X	~RD	~RFSH	~MREQ	~BUSACK
---------------------------------------
0	1	0	1	0
0	1	1	0	0
0	1	1	1	0
1	0	0	1	0
1	0	1	0	0
1	0	1	1	0
1	1	0	1	0
1	1	1	0	0
1	1	1	1	0


Anyone cares to comment? Did I misinterpret something here?

By DamageX

Master (217)

DamageX さんの画像

14-06-2008, 09:28

busreq/busack is for DMA right? is it ever used on MSX?
edit: oops, I see above that it is used for pause button and slow-mo

By dhau

Paragon (1570)

dhau さんの画像

14-06-2008, 09:29

Wow, no help from anyone other then Jipe's automatic translation...

By dhau

Paragon (1570)

dhau さんの画像

14-06-2008, 09:35

There is no DMA on MSX, as far as I know. ~busrq is set low by external devices (like S1985 I assume) to indicate that they need access to addess/data buses. ~busack is set low by Z80 to indicate that cpu is done releasing buses, and external device is free to use it. The reason ~busack is used in Niga's schematics is because he doesn't want to loose refresh signal then user presses STOP button.

By DamageX

Master (217)

DamageX さんの画像

14-06-2008, 09:46

Yes, I believe you're right. Do you have questions about the modification?

By dhau

Paragon (1570)

dhau さんの画像

14-06-2008, 10:51

Well, I was hoping someone can sort of see if my post about how schematics work is making sense. If people help and provide meaningful input, I may share final notes and detailed instructions, once I'm successful.

By DamageX

Master (217)

DamageX さんの画像

15-06-2008, 09:40

I don't see any problems with it, I haven't been able to look at the original though because I have no program that can display a Japanese .DOC file.

The only thing I don't see mentioned is disabling the normal 64KB RAM, which is probably necessary since I'm guessing it is also slot3x.

ページ 2/2
1 |