Made some significant progress with my CPLD experiments:
- Gathered a good set of reference documents on Verilog & VHDL. There are lots of short intro's / tutorials out there, but good reference books are a lot harder to find. It's clear most of this stuff is targeted at professional designers that don't mind paying $ 100+ for a good language reference. And 'open standards': sure, as long as you don't mind paying standards organization like IEEE for a copy (=expensive), or get buy with books based on said standards (which are probably easier to read than those standards, but that's beside the point).
- Worked through the Xilinx ISE in-depth tutorial (all chapters). For anyone considering getting into programmable logic: highly recommended! You basically only need diskspace (no development board required, but a large monitor is helpful), and it gives you a good idea of what's possible / the many steps from idea -> programmed device. In a sense it's a bit like PCB design, not with IC's/pins/circuit traces, but with 'virtual' logic circuitry inside IC's. Many nice-looking screenshot opportunities.
(for pure software ppl: this stuff is probably not for you). - Saw many Verilog & VHDL snippets in the course of that tutorial. Too early to say I can program in either, but reading Verilog or VHDL sources & understand what happens, is getting easier!
- Got my 1st self-designed circuit, with self-chosen I/O pins, onto my CPLD board (a basic inverter, on the board a flashing LED). Done in about 20 minutes using schematic entry. Of course a tiny circuit, but this represents a big milestone for somebody who's never done a CPLD design before.

So basically I've reached the point where I could cook up a circuit from scratch & make a CPLD do that circuit's function. 

Next up: some random logic experiments to become a little more comfortable with the design flow / software.
Considering to do an MSX memory mapper (shouldn't be too hard). Any suggestions for things to try are welcome, as long as it's simple circuits (what you could put together with a couple ~ a dozen 74xx IC's).
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Bitcycle.org - just flipping bits
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): a 44-pin Xilinx XC9536 CPLD, and a 128K SRAM (70 ns) of which I'm using half. Didn't go for a bigger one because I considered it more important to test the function on different systems, than make something more complex, only to find out there's problems with it. SRAM hookup couldn't be simpler: #SLTSL -> #CS, #RD -> #OE, #WR -> #WE, with the CPLD controlling 2 of the higher address lines. Successfully ran some BASIC programs, a few games, and MAPTEST.COM (v4.2 by Maarten Verheijdt & Digital KC) with mapper stuck in below machines:
).