Is the V9938 compatible with SRAM ?

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By Gsparis

Supporter (4)

Gsparis의 아바타

08-03-2007, 10:33

Hi Everyone,

I recently managed to get some V9938 VDP chips and am thinking about making a graphic card for a personal project based on a Z80 architecture.

Since now 80's static RAM chips in DIL package are cheap and still easy to get I would like to use 128Kb single SRAM chip (easy to implement in a design and in a PCB) instead of DRAM chips.

So my question is:
Does the V9938 VDP chip compatible with SRAM only RAM chips and if so, is there any specific ways of connected the VDP chip to the SRAM chips ?

Thanks in advance for the people who will reply.


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By PingPong

Prophet (3839)

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08-03-2007, 14:41

look at the yamaha datasheet

By Gsparis

Supporter (4)

Gsparis의 아바타

08-03-2007, 15:18

Hi PingPong,
Sorry, I should have written that I already read the datasheet about the V9938.
Unfortunately, this datasheet only lists implementations with various DRAM chips.
My question relates to SRAM chips only.

It's because I'm not 100% confident that all I have to do to make it work is just replace DRAM chips by SRAM chips and connect the latter's pins to the VDP that I'm asking for some help or at least confirmation that that's all I have to do !


By flyguille

Prophet (3028)

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08-03-2007, 19:42

with SRAM works for sure.... include is capable to disable the REFRESH cycle with SRAM!

By Gsparis

Supporter (4)

Gsparis의 아바타

08-03-2007, 23:25

include is capable to disable the REFRESH cycle with SRAM!

Sorry I don't understand what your mean by that ?
What is "include" ?


By jltursan

Prophet (2581)

jltursan의 아바타

08-03-2007, 23:50

I guess that flyguille is trying to tell you that using SRAM you can even disable the refresh cycle needed by the DRAM memory

By DamageX

Master (217)

DamageX의 아바타

09-03-2007, 02:29

looks like you will need to latch the address bits 8-15 when RAS goes low

connect (/CAS0 AND /CAS1) to /OE on the SRAM and use one of them for A16 also

By flyguille

Prophet (3028)

flyguille의 아바타

09-03-2007, 03:51

IIRC the vdp has a bit register that if you reset it, the VDP turn off de refresh cycle. (atleas in MSX1's vdp)... so, on a normal MSX1 that means all data gone.... IIRC that also means a terribly hung at BASIC's prompt I really don't know why..... ¿maybe the register table also is erased without refresh?

By Gsparis

Supporter (4)

Gsparis의 아바타

09-03-2007, 08:37

Flyguille, I re-read the datasheet of the V9938 but I don't see anything about the disabling of the refresh function.
I will check this on the V9918. Maybe it does exist but isn't documented so the V9918 datasheet might be of help.

DamageX, you're right !
I need to demultiplex the data bus (I guess with a 74HC373 octal latch IC) in order to get the misssing A8-A15 address bits with the help of CAS0 or CAS1 (I need to check which of them must be used as /OE and A16).

Also, it seems I need to adjust VR to get a straight A8-A15 correspondance from the demultiplexed data bus AD0-AD7.

If anybody knows any details, I'd be grateful to share your knowledge.

By Leo

Paragon (1236)

Leo의 아바타

29-07-2009, 15:04

@gsparis did you manage to connect tha sram to vdp ?

By RetroTechie

Paragon (1563)

RetroTechie의 아바타

29-07-2009, 20:34

You might be interested in a (ZX Spectrum) hardware project I published recently. It deals with the exact same problem, but uses a single 32KB SRAM as replacement for 8 pieces of 16K x 1 bit DRAM:

It's well documented, schematics and all. I've built it into just 2 Spectrums so far, but operation is perfect - no difference with original machines can be detected.

For the V9938, you could (try to) use the exact same principle, just with a few more address bits. Some of the nitty gritty:

  • Obviously, for the V9938 you'd have not 7, but 8 multiplexed address lines (so all bits of an 8-bit latch).
  • You use a register that is clocked on the high-to-low transition of the /RAS signal. So not a 373 (it's level-triggered), but a 374 for example, or 574 (same function but easier pin layout). Since the 374/574 are clocked at low-to-high edge, you need to invert the /RAS signal (see schematic).
  • Think of the /CAS signals as a /Chip Select, and use as such. For the V9938, you could put /CAS0 and /CAS1 through an AND gate (works as OR for active-low signals), and connect output to SRAM's /CS line. It would then go low if /CAS0 or /CAS1 goes low. I think you may get away with it if you then use either /CAS0 or /CAS1 as highest SRAM address line. For first experiments: connect highest SRAM address to either +5 or GND, use only /CAS0 directly as /CS signal, and try lower screen modes (64K VRAM).
  • You connect SRAM's /OE signal directly to ground. The /CS triggers read/write action, the /WE decides which. See description / SRAM datasheets for details.
  • Reading or writing may still occur after /RAS goes high (inactive), if /CASx remains low. This is intended behaviour!

(..) but I don't see anything about the disabling of the refresh function.
Refresh just clocks the address latch: ignore LOL! (see description).

Also, it seems I need to adjust VR to get a straight A8-A15 correspondance from the demultiplexed data bus AD0-AD7.
Again: ignore. For SRAMs, individual address lines have no special meaning or difference with other address lines (there's no rows or columns in a functional sense). Just use what you like / what is easiest to wire up.

Oh and: whatever applies to the TMS9918(A), does not to the V9938! The memory interface was completely re-done for the latter (due to higher bandwith, VDP commands etc.). Also: if you have something that works on the V9938 (MSX2), I'm 99,9% confident it would work on the V9958 (MSX2+) as well. Memory interface and timing is very similar between these.

Last but not least: if you try anything, please report your findings?

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