VG8020/40 Replace 32k Rom with 64k EProm

Door AxelF

Champion (339)

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30-12-2018, 15:23

I have replaced the 32k ROM with a 64k EProm (With IC socket)
The Eprom is programmed with the first 32k from the original ROM and the rest is filled with $E5
I'm trying to use the extra 32k (of the 64k eprom) to store some data.

I solderd a wire from pin A15 of the eprom to pin A15 of the Z80 CPU this Eprom pin is not in the socket.
I also solderd a wire from GND to Chip Enabled pin (Always On)

The MSX boots normal but when i look in to the data with a Memory monitor
all data from $0000 to $7fff is OK (like the original 32k ROM)
all data above $8000 is garbled (not $E5 as i have programmed it)

Can someone tell me what i did wrong here, do i need the CS12 signal?

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Van Alexey

Guardian (2178)

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30-12-2018, 17:43

If you want to use the entire subslot's address space for the EPROM, you need the RD signal, not CS. Also in some cases the 16kb parts of the ROM could be swapped, but when you use the RD signal - the image in the EPROM will be mirrored to the address space "as is".

Van AxelF

Champion (339)

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30-12-2018, 19:38

Thanks for your help,

This is the current situation

Wire 1 - from EPROM (CE signal) to Z80 (RD signal)
Wire 2 - from EPROM (A15) to Z80 (A15)

Unfortunately it is not working, the MSX boots normal
data above $8000 is still garbled.

Van Alexey

Guardian (2178)

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30-12-2018, 21:28

You should connect the OE to RD and CE should be left as it was - in the socket.

Van AxelF

Champion (339)

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30-12-2018, 23:06

Thanks again Alexey,
Connected OE to RD and put CE back in socket, unfortunately to no avail.
Still boots but garbage @8000

Did some tests with this configuration in OpenMSX, it worked perfectly.
Reading thru the service manual, right now.. any tips are welcome.

Van RetroTechie

Paragon (1554)

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31-12-2018, 02:36

AxelF wrote:

Reading thru the service manual, right now..

What service manual? For the VG8020/00? That's a very different machine from the /40 you have in front of you. S-3527 datasheet and some pcb track following will be more helpful.

Alexey wrote:

If you want to use the entire subslot's address space for the EPROM, you need the RD signal, not CS.

For this purpose, you would need a /SLT0 slot select signal - which the S-3527 doesn't output. /ROMCS is only activated for the lower half of slot 0.

See "Memory maps and expansion" in the S-3527 datasheet. With slot 3 expanded (as in the /40), there's only /CAS3 to activate memory in C000-FFFFh area of slot 0. Nothing for 8000-BFFFh area in that slot.

Read: you'd need to add some logic to combine /ROMCS and /CAS3. Like an AND gate (works as OR for active-low signals), output wired to the EPROM's /CS pin, and the EPROM's /OE wired to Z80 /RD signal. Then you'd have the EPROM fill slot 0 except 8000-BFFFh area (so only 48KB mapped). No guarantee this would work though... Some other options:

  • 'Snoop' on Z80 writes to the primary slot select register, and produce a /SLT0 select signal from that. Would require quite a bit of logic, CPLD or similar - obviously over your head.
  • Map the other half of the EPROM into some other slot, like 3-0, 3-1 or 3-3. Multiple options in what memory range in such slot, but again: needs extra logic.
  • Put some kind of block-switching in place for the 0000-7FFFh area the regular BIOS is in. Again: extra logic.

What you have in mind for use of this extra ROM? Likely there's more convenient options for that: addition of a write protected SRAM (battery backed?), EEPROM, or even an FRAM chip (= RAM chip whose contents survives a power cycle).

Van AxelF

Champion (339)

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31-12-2018, 16:11

Thanks for clearing things out RetroTechie,

Maybe i should consider piggybacking a 16/32k eprom on top of the original rom,
and hook it up to slot 3-0, i guess this needs the least amount of extra logic ?

Van Alexey

Guardian (2178)

afbeelding van Alexey

02-01-2019, 13:15

RetroTechie wrote:

For this purpose, you would need a /SLT0 slot select signal - which the S-3527 doesn't output. /ROMCS is only activated for the lower half of slot 0.

Hmmm, I was not aware of that, sorry. I revisited the schematics of our hardware and it is true that CS should be replaced with the corresponding SLTSEL signal together with OE connected to RD (for the full slot).