Is the V9938 compatible with SRAM ?

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Van msxegor

Master (183)

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15-12-2010, 08:46

Hi! I'm recently resurrecting Yamaha YIS-503II (the same motherboard as YIS-604 and CX-7, MSX-1 with V9938). Since 4164 DRAMs are hard to find, i tried out SRAM setup and it works. HC373 is used for latch оn low RAS. CAS goes to one of SRAM address lines for bank select.

Schematic can be found here: http://content.foto.mail.ru/mail/voznyak/etcetera/s-747.png
NB: address and data lines mixed for single-side board layout

Van Leo

Paragon (1236)

afbeelding van Leo

15-12-2010, 19:22

thanks, for sharing , i have also a pair of V9958 left and srams.

Van mohai

Paladin (932)

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15-12-2010, 21:19

Nice!
I understand almost everything in the schematics but,
Why did you connect /CAS line to A8?
By the way, V9938 has 3 /CAS lines (if i am not wrong): /CAS0 /CAS1 and /CASX. Which one to use?

I think your schematic should not work because:

- VDP sets data on data bus (if write)
- VDP sets row address and lowers RAS, (address signals, lower 8 bit)
- VDP sets collumn address and lowers CAS, (address signals, higher 8 bit)

If i am not wrong, that means that HC373 is properly connected but, on the second cycle, CAS should activate CE (not RAS), to put all 16 bit address to SRAM lines.

... but you said it DOES work ... i am confused Question

Van Lord_Zett

Paladin (807)

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15-12-2010, 23:58

i am confused to... but thats normal

Van JINsMac

Expert (77)

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16-12-2010, 00:32

msxegor // thank you sharing, I have a yis503m I'll test that.

Van Leo

Paragon (1236)

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16-12-2010, 04:20

@mohai:

- cas on a8 is normal :
on sram chip you need to decode 128kb ram space and in dram design you have 2 banks of 64kb .
the selection between each 64kb with cas in dram design can be understood in the sram design as a high address decode between high and low part of the 128kb adress space.
it would be clearer if cas was on a16 , but on a8 it works as well , maybe just easier to route on single sided pcb.
you can use either cas0 or cas1 , it does not matter, casx not to be used.

- ras on CS will work since it stays low during all 2 cycle, even the second.

- for databus i guess that /WR signal on the sram overides the /OE low for databus direction
so /WE low + /OE low makes I/O bus of sram input
...
i have just checked 621024 datasheet it is like this :
if /WE is low then no matter the value on /OE the data bus is input for the sram and it will
then allow vdp to set its value to write .

Van msxegor

Master (183)

afbeelding van msxegor

16-12-2010, 08:42

Some extra notes:
- SRAM /CS can be grounded, since we have a single chip. This will cause a slight increase in power consumption but still it will be probably less than with DRAMs
- yes, /WE has priority over /OE, at least on 62xx, Samsung K6x and modern Cypress SRAMs
- I used 70ns SRAM, and it seems to work, but since it is replacement for two interleaved 120ns DRAM banks - I recommend 55ns or faster
- My schematic does not detect /CASX access. However I know only a single program that used ERAM, an old MSXDOS1 ramdisk program, so this is probably not a problem at all. To ignore ERAM access, simply connect second (positive) chip select (pin 30 of 621024) to /CASX instead of VCC.

Van Gregory

Master (178)

afbeelding van Gregory

06-08-2021, 11:47

RetroTechie wrote:

You might be interested in a (ZX Spectrum) hardware project I published recently. It deals with the exact same problem, but uses a single 32KB SRAM as replacement for 8 pieces of 16K x 1 bit DRAM:

bitcycle.org/retro/spectrum/SRAM_replacement/

It's well documented, schematics and all. I've built it into just 2 Spectrums so far, but operation is perfect - no difference with original machines can be detected.

For the V9938, you could (try to) use the exact same principle, just with a few more address bits. Some of the nitty gritty:

  • Obviously, for the V9938 you'd have not 7, but 8 multiplexed address lines (so all bits of an 8-bit latch).
  • You use a register that is clocked on the high-to-low transition of the /RAS signal. So not a 373 (it's level-triggered), but a 374 for example, or 574 (same function but easier pin layout). Since the 374/574 are clocked at low-to-high edge, you need to invert the /RAS signal (see schematic).
  • Think of the /CAS signals as a /Chip Select, and use as such. For the V9938, you could put /CAS0 and /CAS1 through an AND gate (works as OR for active-low signals), and connect output to SRAM's /CS line. It would then go low if /CAS0 or /CAS1 goes low. I think you may get away with it if you then use either /CAS0 or /CAS1 as highest SRAM address line. For first experiments: connect highest SRAM address to either +5 or GND, use only /CAS0 directly as /CS signal, and try lower screen modes (64K VRAM).
  • You connect SRAM's /OE signal directly to ground. The /CS triggers read/write action, the /WE decides which. See description / SRAM datasheets for details.
  • Reading or writing may still occur after /RAS goes high (inactive), if /CASx remains low. This is intended behaviour!

(..) but I don't see anything about the disabling of the refresh function.
Refresh just clocks the address latch: ignore LOL! (see description).

Also, it seems I need to adjust VR to get a straight A8-A15 correspondance from the demultiplexed data bus AD0-AD7.
Again: ignore. For SRAMs, individual address lines have no special meaning or difference with other address lines (there's no rows or columns in a functional sense). Just use what you like / what is easiest to wire up.

Oh and: whatever applies to the TMS9918(A), does not to the V9938! The memory interface was completely re-done for the latter (due to higher bandwith, VDP commands etc.). Also: if you have something that works on the V9938 (MSX2), I'm 99,9% confident it would work on the V9958 (MSX2+) as well. Memory interface and timing is very similar between these.

Last but not least: if you try anything, please report your findings?

Unfortunately the link doesn't work anymore, is there another way to get the info on your project?

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