Curiosity about CS1 CS2 and CS1/2 in ROM SLOT CONNECTOR...

Door friguron

Master (169)

afbeelding van friguron

14-07-2020, 16:41

Hi,

I'm slowly entering into the hardware world of MSX, I always felt it was a martian thing, made only for hardware guru's and so on... But little by little, and reading some good info and pdf's around, I'm getting used to the language spoken in said documents. Schematics, PCB's, etc...

The other day I came accros this document about some primitive KONAMI 4 rom mapper

https://hansotten.file-hunter.com/uploads/files/MapperMSXKon...

In this apparently simple schematic, everything seems easy and understandable, so I started to implement something real with it, but then suddenly I came accross something:

-In all three schematics included inside the pdf file no one speaks about CS1 CS2 and CS1/2 lines (and maybe some other lines either)... What's the expected connection for these 3 (or more) lines inside a KONAMI 4 (or whatever mapper) mapped rom PCB? Where should we connect them, if ever?
as far as I understand the one I should care about should be CS1/2, but then I have no idea about where to connect it against. OE of the EEPPROM IC maybe? (No idea, I'm kind of new to these kind of PCB lines)

Thanks in advance, if my doubts are unclear, please ask me for more info.

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Van lintweaker

Champion (311)

afbeelding van lintweaker

14-07-2020, 17:05

Hi,

CS1/CS2 and CS12 are chip select lines for ROMs. /CS1 selects page 1 (04000-7fffh) and /CS2 selects page 2 (8000-0bfffh). /CS12 is used for ROMs using both page 1 and 2.
For ROMs with mappers, mostly the slot select signal /SLTSL with additional logic for setting the ROM page to use.
Note: /CS1,/CS2 and /CS12 signals should always be used in combination with /SLTSL.

Van friguron

Master (169)

afbeelding van friguron

14-07-2020, 17:47

My specific question was about the exact 3 circuits appearing on the pdf I linked, not the generic theory (which I think I already knew).

I assume that for a megarom mapped eeprom, again, like the one in the circuit, the important line of these 3 should be /CS12 (a megarom typically has page 1 and 2 connected), and still, I don't get where onto the simple mapper logic already appearing in the pdf I should logically connect it to.
/SLTSL seems to be already used, all good, but CS** apparently not...

It seems the author forgets about /CS12 or assumes the good electronic engineer knows about this low level stuff, and he focuses onto the mapper circuit.

EDIT: or maybe when dealing with megarom PCB's /CS1, /CS2 and /CS12 should all 3 be ignored in favour of just /SLTSL ? (Unsure about that)

Van lintweaker

Champion (311)

afbeelding van lintweaker

14-07-2020, 17:46

Using /SLTSL to select a ROM makes it start at 0000h. The 670 does the magic of paging in 8kb blocks.
Page 0 of the ROM is probably not used.

Van friguron

Master (169)

afbeelding van friguron

14-07-2020, 17:56

lintweaker wrote:

Using /SLTSL to select a ROM makes it start at 0000h. The 670 does the magic of paging in 8kb blocks.
Page 0 of the ROM is probably not used.

And what about CS1 CS2 and CS12, which were the thing I asked about? Can I deduct they can be ignored if the only line used int that circuit seems to be /SLTSL ?
Is a rom PCB valid when it has all 3 /CS1 /CS2 /CS12 lines disconnected? (No idea)

BTW, peeking Nemesis 3 original ROM, I can see many disconnected pads against the MSX connector, mainly on the right part looking it from the front... As far as I can detect, it only has /CS12 and /SLTSL connected (pins 3 and 4), ALL other lines next to these are just non existent... So /CS12 must be used for some chip enable line inside the ROM I suppose...

I will investigate more

Van Fabf

Master (247)

afbeelding van Fabf

14-07-2020, 21:28

lintweaker wrote:

Note: /CS1,/CS2 and /CS12 signals should always be used in combination with /SLTSL.

Are you sure ?
How do you proceed with /CE /OE and /WR ?
I always do like this :

Van friguron

Master (169)

afbeelding van friguron

14-07-2020, 22:06

One of my doubts is not knowing what the runtime electronic engine of an MSX does in terms of /SLTSL or /CS** whenever it wants to access to a certain ROM address byte: Does /SLTSL get always active for the wanted slot? if so, are CS1/2/12 lines redundant, specially if you manage to build a megarom mapper circuitry before accessing the EEPROM itself?
(For example I will be wanting to use a 512 KBytes one... XXX040, not a C128 or C256 small one...)

After studying the schematics, my HW newbie instinct feels that if /SLTSL is active for every access to certain slot, and this opens "free access to its raw 64 KB's starting from 0x0000" you can manage to access to pages 1 and 2 with the proper mapper circuitry, thus "ignoring" CS1/2/**, as apparently seems to do the .pdf I linked in my first post...

Is my instinct right?

Van lintweaker

Champion (311)

afbeelding van lintweaker

15-07-2020, 08:51

Fabf wrote:
lintweaker wrote:

Note: /CS1,/CS2 and /CS12 signals should always be used in combination with /SLTSL.

Are you sure ?
How do you proceed with /CE /OE and /WR ?
I always do like this :

For a ROM /WR is not used (can be used for flash). /CE should be connected to /SLTSL or combination of /SLTSL and /CS1,/CS2 etc depending on what you want to achieve. /OE should be connected to /RD.
Putting /CE to ground means it is always enabled even when not used. I would not recommend that.

Van ducasp

Champion (386)

afbeelding van ducasp

15-07-2020, 13:34

friguron wrote:

Hi,

I'm slowly entering into the hardware world of MSX, I always felt it was a martian thing, made only for hardware guru's and so on... But little by little, and reading some good info and pdf's around, I'm getting used to the language spoken in said documents. Schematics, PCB's, etc...

The other day I came accros this document about some primitive KONAMI 4 rom mapper

https://hansotten.file-hunter.com/uploads/files/MapperMSXKon...

In this apparently simple schematic, everything seems easy and understandable, so I started to implement something real with it, but then suddenly I came accross something:

-In all three schematics included inside the pdf file no one speaks about CS1 CS2 and CS1/2 lines (and maybe some other lines either)... What's the expected connection for these 3 (or more) lines inside a KONAMI 4 (or whatever mapper) mapped rom PCB? Where should we connect them, if ever?
as far as I understand the one I should care about should be CS1/2, but then I have no idea about where to connect it against. OE of the EEPPROM IC maybe? (No idea, I'm kind of new to these kind of PCB lines)

Thanks in advance, if my doubts are unclear, please ask me for more info.

Those lines are mostly used.by cartridges that are up to 32KB and they exist to lower the cost of smaller cartridges, as with that you do not need to mind mirroring and can make sure a cartridge is in the proper page (I.e: 8000 for a basic program in cartridge, or 4000 for a 16K ASM program, or 4000-BFFF for a 32K ASM program. As the general idea was that most cartridges would need BIOS in page 0 and that page 3 has system variables that someone shouldn't page out while using BIOS for most cases, it made a lot of sense, TTL chips costs money and by the 80s, more than now.

Why a mapper wouldn't use it then? For two reasons, most likely, being the first that if it is a game that already implement bank switching (mapper), you might not need to use those signals at all, your mapper is already taking care of more advanced address decoding/encoding to map regions of the memory. Another reason is that mirroring might be desirable in some cases:

https://www.msx.org/wiki/MegaROM_Mappers#Konami.27s_MegaROMs...

It could be intentionally used having the content spread over different pages or just that, since the rom game in Konami mapper was running all alone and they had spent logic to map, they did not want to spend more money and making a more complex mapper that used csX signals to avoid mirroring...