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What is the point of bits [3:0] in the R15 of the PSG

by Eugeny_Brychkov on 05-12-2019, 17:56
Score: 160.48 %, Type: Forum topic , Comments: 9 comments
Never touched joystick circuitry too deeply. Looking into the book page 26 I can not get what is the purpose of the IOB0-IOB3 and their connection to the inputs of the port A. Somewhere else I ... IOA5/IOA6 input pins and the IOB0-3 output pins. Normally the outputs are set to 1 by the BIOS ISR to allow ...

Please try [GR8NET] + [MFR SCC+ SD] in Panasonic FS-A1WSX

by Eugeny_Brychkov on 18-10-2018, 21:21
Score: 153.51 %, Type: Forum topic , Comments: 6 comments
I have a report from the owner of the all three devices that they do not work when all are being employed. When GR8NET and MFR are inserted into the machine, machine behaves weirdly restarting and rebooting, but sometimes works properly after ...

IORQ active, others not active

by Eugeny_Brychkov on 24-12-2016, 00:58
Score: 144.17 %, Type: Forum topic , Comments: 2 comments
I am experimenting with my machine, and it appears to have IORQ active for long time - at least 280 ns, with RD and WR being inactive. I can not have picture of M1, because it is just not routed to the board. However M1+IORQ situation is only possible (according to Z80 manual) in IM0 mode as interrupt ...

HB-501P (MSX1) port I/O issue

by Eugeny_Brychkov on 20-10-2016, 21:04
Score: 143.54 %, Type: Forum topic , Comments: 17 comments
(+5V) or down (0V) but hardware that uses open collector logic can only drive the bus down or leave ... Without this the state will be most probably floating somewhere between 0V and +5V computer can see it as bit 0 or 1 depending of what color socks you are wearing. It is indeed true that adding 10K ...

Zemmix Neo (and probably OCM) issue

by Eugeny_Brychkov on 20-04-2016, 17:52
Score: 141.41 %, Type: Forum topic , Comments: 17 comments
(0.5 T-cycle) after IORQ activates and ends with IORQ; WR: port data write Situation is the same as with port read: for OCM activtion of WR signal is delayer by 0.5 T-cycles. My ... write 0.5 T-cycles later than Z80. MSX cardridge port signals MSX cardridge port signals ...

Ports A4-A7 returning non-FF

by Eugeny_Brychkov on 29-07-2015, 00:24
Score: 138.2 %, Type: Forum topic , Comments: 11 comments
for I/O devices decode all Address lines but A2, A1 and A0. So each device is given an eight ports range, ... and A0. So each device is given an eight ports range, as flyguille mentioned. The only MSX computers ...

R800 article issue in describing Z80 timing.

by Eugeny_Brychkov on 06-08-2014, 13:16
Score: 134.36 %, Type: Forum topic , Comments: 1 comment
Hello all, I have just put warning notice to [url=https://en.wikipedia.org/wiki/R800_(CPU)]this[/url] article which describes Z80 instruction fetch machine cycle as Quote: Z80, cycle 1: set the higher 8-bits of address Z80, cycle 2: set the lower 8-bits of address Z80, cycle 3: waitstate Z80, ...

RTC alarm function

by Eugeny_Brychkov on 26-02-2012, 21:36
Score: 126.21 %, Type: Forum topic , Comments: 2 comments
Hello guys, anyone knows if alarm function was ever supported on the MSX2/MSX2+/MSX Turbo? In other words - can I reuse alarm space to store some data without worrying to get it back corrupt? Thanks. AFAIK, probably on all of AFAIK, ...

VSYNC/HSYNC from VDP

by Eugeny_Brychkov on 17-06-2011, 23:33
Score: 124.2 %, Type: Forum topic , Comments: 3 comments
Hello guys, anyone has experience getting / deriving separate sync signals from V9938? HSYNC ~ 15KHz VSYNC ~ 50 or 60 Hz What I am interested is connecting the stuff to CGA monitor. Is that possible? yes it is , but CGA is digital input, ...

21.480?

by Eugeny_Brychkov on 15-06-2011, 15:39
Score: 124.15 %, Type: Forum topic , Comments: 2 comments
Anyone tried to use 21.480MHz oscillator in their machines? Error comparing to standard 21.47727 is just 0.012%... [quote]Anyone tried to use 21.480MHz oscillator in their mac Anyone ... 0.012%... for vdp? there should be, i the yamaha v9938 datasheet then min,max,typ value of each ...
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