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Flappy Bird on MSX1

by Metalion on 01-03-2014, 09:34
Score: 129.15 %, Type: Forum topic , Comments: 95 comments
(playable): http://www.msx.org/news/software/en/mega-challenge-09-leda Only the environment stuff ... For the Ti99 already exists! For the Ti99 already exists! http://youtu.be/0Uph0 ... https://www.youtube.com/watch?v=wuoCeze0B3c now this one ? Very nice!!!! Very nice!!!! Congratulations! Wow! A scroll down ...

Extra WAIT signal on all instructions ?

by Metalion on 26-01-2014, 09:55
Score: 125.22 %, Type: Forum topic , Comments: 16 comments
Hi everyone, Reading the Z80 documentation, I'm wondering if the extra WAIT signal is used on every instruction. There's a first WAIT signal poll from the CPU on fetching the instruction from memory, but that seems to be included in the M1 ...

RLD and RRD instructions

by Metalion on 24-01-2014, 14:28
Score: 125.26 %, Type: Forum topic , Comments: 4 comments
Output HEX(HL) -> SCREEN xor a rld call .Nibble .Nibble: push af daa add a,F0h adc a,40h call ... to convert Bin2Hex: ld b,a rrca rrca rrca rrca and 0Fh ; These instructions are the important ones cp 10 ; sbc a,69h ; daa ; ld (hl),a inc hl ld a,b and 0Fh cp 10 sbc a,69h daa ld ...

Respecting the 29 T-states timing

by Metalion on 22-01-2014, 08:58
Score: 125.67 %, Type: Forum topic , Comments: 31 comments
b,0 loop: outi jp nz,loop Do I respect the VDP timing requirement of 29 T-states ... everyone, If I use this code on MSX1 to transfer 256 bytes to VRAM : ld b,0 loop: outi ... http://www.msx.org/forum/semi-msx-talk/emulation/msx-easier-... , it seems to be the case. @Metalion, yes, MSX1 in blank @Metalion, yes, MSX1 ...
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