VDP Command Registers
This page was last modified 18:22, 31 January 2022 by Bitsofbas. Based on work by Mars2000you and Gdx.

Contents

The command registers

The last fifteen registers of the VDP are used for the execution of simple graphic commands such as copy, drawing of line/point/rectangle, etc. These registers can only be written. MSX-BASIC instruction VDP() uses the values 33 to 47 (values are shifted by one) to access them. Reading is not possible.

Registers 32 and 33

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#32 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 (MSX2/2+/Turbo R)
R#33 0 0 0 0 0 0 0 SX8 (MSX2/2+/Turbo R)

These registers contain the source horizontal coordinate of graphical commands listed below.

Register 32 contains the least signifiant 8 bits and register 33 the most signifiant bit (SX8) located on the bit 0.

So this coordinate can vary between 0 and 255 on screens 5, 8, 10 to 12, between 0 and 511 on screens 6 and 7.

Note that on screens 5 and 7, the lower one bit, and on screen 6, the two lower bits are lost with the High Speed Move commands.

These registers are used when executing one of these commands:

  • HMMM (High Speed Move VRAM to VRAM)
  • LMCM (Logical Move VRAM to CPU)
  • LMMM (Logical Move VRAM to VRAM)
  • SRCH
  • POINT

Registers 34 and 35

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 (MSX2/2+/Turbo R)
R#35 0 0 0 0 0 0 SY9 SY8 (MSX2/2+/Turbo R)

These registers define the source vertical coordinate of graphical commands listed below.

Register 34 contains the least signifiant 8 bits and register 35 the most signifiant two bits (SY8 & SY9) located on the bits 0 and 1.

You can thus consider that register 35 corresponds to the page number in VRAM.

Note that on screens 5 and 7, the lower one bit, and on screen 6, the two lower bits are lost with the High Speed Move commands.

These registers are used when executing one of these commands:

  • YMMM (High Speed Move VRAM to VRAM on same Y coordinate)
  • HMMM (High Speed Move VRAM to VRAM)
  • LMCM (Logical Move VRAM to CPU)
  • LMMM (Logical Move VRAM to VRAM)
  • SRCH
  • POINT

Registers 36 and 37

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 (MSX2/2+/Turbo R)
R#37 0 0 0 0 0 0 0 DX8 (MSX2/2+/Turbo R)

These registers define the destination horizontal coordinate of graphical commands listed below.

Register 36 contains the least signifiant 8 bits and register 37 contains the most signifiant bit (DX8) located on the bit 0.

So this coordinate can vary between 0 and 255 on screens 5, 8, 10 to 12, between 0 and 511 on screens 6 and 7.

These registers are used when executing one of these commands:

  • HMMC (High Speed Move CPU to VRAM)
  • YMMM (High Speed Move VRAM to VRAM on same Y coordinate)
  • HMMM (High Speed Move VRAM to VRAM)
  • HMMV (High Speed Move VDP to VRAM)
  • LMMC (Logical Move CPU to VRAM)
  • LMMM (Logical Move VRAM to VRAM)
  • LMMV (Logical Move VDP to VRAM)
  • LINE
  • PSET

Registers 38 and 39

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 (MSX2/2+/Turbo R)
R#39 0 0 0 0 0 0 DY9 DY8 (MSX2/2+/Turbo R)

These registers define the destination vertical coordinate of graphical commands listed below.

Register 38 contains the least signifiant 8 bits and register 39 the most signifiant two bits (DY8 and DY9) located on the bits 0 and 1.

So this coordinate can vary between 0 and 1023 on screens 5 and 6, between 0 and 511 on screens 7, 8, 10 to 12.

You can thus consider that register 38 corresponds to the page number in VRAM.

These registers are used when executing one of these commands:

  • HMMC (High Speed Move CPU to VRAM)
  • YMMM (High Speed Move VRAM to VRAM on same Y coordinate)
  • HMMM (High Speed Move VRAM to VRAM)
  • HMMV (High Speed Move VDP to VRAM)
  • LMMC (Logical Move CPU to VRAM)
  • LMMM (Logical Move VRAM to VRAM)
  • LMMV (Logical Move VDP to VRAM)
  • LINE
  • PSET

Registers 40 and 41

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 (MSX2/2+/Turbo R)
R#41 0 0 0 0 0 0 0 NX8 (MSX2/2+/Turbo R)

These registers specify the number of dots on the horizontal axis (the width of the area to be traced) for internal VDP commands listed below.

In the case of the LINE command, see the register 45 description below!

Register 40 contains the least signifiant 8 bits and register 41 contains the most signifiant bit (NX8) located on the bit 0.

Note that on screens 5 and 7, the lower one bit, and on screen 6, the two lower bits are lost with the High Speed Move commands.

These registers are used when executing one of these commands:

  • HMMC (High Speed Move CPU to VRAM)
  • HMMM (High Speed Move VRAM to VRAM)
  • HMMV (High Speed Move VDP to VRAM)
  • LMMC (Logical Move CPU to VRAM)
  • LMCM (Logical Move VRAM to CPU)
  • LMMM (Logical Move VRAM to VRAM)
  • LMMV (Logical Move VDP to VRAM)
  • LINE


Registers 42 and 43

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 (MSX2/2+/Turbo R)
R#43 0 0 0 0 0 0 NY9 NY8 (MSX2/2+/Turbo R)

These registers specify the number of dots on the vertical axis (the height of the area to be traced) for VDP commands listed below.

In the case of the LINE command, see the register 45 description below!

Register 42 contains the least signifiant 8 bits and register 43 contains the most signifiant two bits (NY8 & NY9) located on the bits 0 and 1.

These registers are used when executing one of these commands:

  • HMMC (High Speed Move CPU to VRAM)
  • YMMM (High Speed Move VRAM to VRAM on same Y coordinate)
  • HMMM (High Speed Move VRAM to VRAM)
  • HMMV (High Speed Move VDP to VRAM)
  • LMMC (Logical Move CPU to VRAM)
  • LMCM (Logical Move VRAM to CPU)
  • LMMM (Logical Move VRAM to VRAM)
  • LMMV (Logical Move VDP to VRAM)
  • LINE


Register 44

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#44 CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 (MSX2/2+/Turbo R)

This register specifies tracing color.

Bits CL0 to CL7 encode the color in screens 8, 10/11 and 12. Bits CL4 to CL7 are ignored in other screen modes.


Register 45

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#45 0 MXC MXD MXS DIY DIX EQ MAJ (MSX2/2+/Turbo R)

This register specifies tracing color.

  • MAJ must specify the longest side. 0 for horizontal, 1 for vertical. (Used only by the LINE command.)
  • EQ = 0 to stop the search when the color is found, 1 to stop the search when the color is different from that set.
  • DIX = When this bit is at 1, the horizontal displacement value (register 40 and 41) comes negative. The displacement goes to the reverse direction.
  • DIY = When this bit is at 1, the vertical displacement value (register 42 and 43) is considered negative. The movement is in the other direction.
  • MXS = Source video memory. 0 for main VRAM; 1 for extended VRAM (for MSX with 192 KB of VRAM).
  • MXD = Destination video memory. 0 for main VRAM; 1 for extended VRAM (for MSX with 192 KB of VRAM). This functionality has not been integrated into the MSX standard.
  • MXC = RAM / VRAM switching. 1 for RAM extension; 0 for VRAM. Unused on MSX, reset this bit always.


Register 46

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R#46 CM3 CM2 CM1 CM0 LO3 LO2 LO1 LO0 (MSX2/2+/Turbo R)

This register specifies the logical operator to use (LO3-LO0) and the command to execute (CM3-CM0).

A write to this register executes the command!