VDP Display Registers
This page was last modified 16:25, 10 August 2022 by Gdx. Based on work by Mars2000you.

Contents

Control Register 13

In 80 column text mode, this register is used to set the times of the periods of blinking of text colors. The text color defined by register 13 is displayed during the first period. The current color is displayed during the second period.

In graphic modes, this register is used to configure a cycle of two display periods of an even or odd page. The lower even page is displayed during the first period of the cycle. The odd page or the alternation of the two pages if bit E0 of register 9 is set, is displayed during the second period.

This register can be only written. Use the MSX-BASIC instruction VDP(14) to access it. The instruction reads the system variable REG14SAV (0FFECh) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#13: ON3 ON2 ON1 ON0 OF3 OF2 OF1 OF0 (MSX2/2+/Turbo R)
  • ON0-ON3 bits set the time for the second period.
Length of a period in seconds for a frequency of 50 Hz:
0000 = 0.0 0001 = 0.2 0010 = 0.4 0011 = 0.6
0100 = 0.8 0101 = 1.0 0110 = 1.2 0111 = 1.4
1000 = 1.6 1001 = 1.8 1010 = 2.0 1011 = 2.2
1100 = 2.4 1101 = 2.6 1110 = 2.8 1111 = 3.0
  • OF0-OF3 bits set the time for the first period and enables the periodic display when any of these bits are set to 1.

Procedure in 80 column text mode:

  1. Specify the text colors for the first period in the register 7.
  2. Specify the text colors for the second period in the register 12.
  3. Modify the color table in VRAM. This table occupies 240 bytes (0800h to 08EFh by default), each bit corresponds to character (24 lines × 80 columns = 1920 characters, hence 1920 bits, or 240 bytes). If the bit is at 1, the character flashes with the colors defined by registers 7 and 12, while if it is at 0, the character does not flash. It keeps the color of register 7.
  4. Set register 13 with the correct display times.

Procedure in graphic mode (SCREEN 5 to 12):

Graphic pages come in pairs. In SCREEN 5 and 6, you can choose to display alternately pages 0 and 1 or 2 and 3 but never 0 and 3, 1 and 3 or 0 and 2.

  1. Set bits N10 to N14 of register 2, in order to display an even page.
  2. Set the respective display times and activate the periodic display using register 13.
  3. Set bit E0 of register 9 to 1 to activate the alternation of 2 pages on the second period.


Control Register 18

This register can be only written. Use the MSX-BASIC instruction VDP(19) to access it. The instruction reads the system variable REG18SAV (0FFF1h) to return the requested value. It corresponds to the SET ADJUST instruction of MSX-BASIC, but without saving in the Real Time Clock (RTC).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#9: V3 V2 V1 V0 H3 H2 H1 H0 (MSX2/2+/Turbo R)
  • V0-V3 bits serve to adjust the screen vertical location. (0 at initialisation)
  • H0-H3 bits serve to adjust the screen horizontal location. (0 at initialisation)

Please wait for the CE bit of status register 2 is reseted before accessing this register when the display of the screen or Sprites are deactivated otherwise VRAM corruption could occur.

Using this register to make screensplits can lead to uncommon results when the sprites are disabled. For example, the background color will be used for the current line by moving the screen to the left with control register 18.


Control Register 19

This register can be only written. Use the MSX-BASIC instruction VDP(20) to access it. The instruction reads the system variable REG19SAV (0FFF2h) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#19: IL7 IL6 IL5 IL4 IL3 IL2 IL1 IL0 (MSX2/2+/Turbo R)
  • This register defines the line number where a programmed interrupt must happen when horizontal retrace interrupts are enabled (value 1 in bit 4 - IE1 - of control register 0).

The VDP will generate interrupt when it starts to display the scan line corresponding to the value written in control register 19. It will also set to 1 bit 0 - FH - of status register 1.


Control Register 23

This register can be only written. Use the MSX-BASIC instruction VDP(24) to access it. The instruction reads the system variable REG23SAV (0FFF6h) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#23: DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 (MSX2/2+/Turbo R)
  • This register sets the value of the first line to display on the screen.

Virtual screen size is 256 lines (0 to 255), visible vertical screen size can be 192 or 212 depending of bit 7 - LN - of control register 9. By default, value of this register is 0 and lines 0 to 191 or 211 are displayed. Setting another value than zero creates a vertical offset, displaying un-initialized parts of the VRAM which may look as garbage.

Display of virtual screen is made in cycle: if you increase the value in this register, top of virtual screen will appear at the bottom of the visible screen. This trick can be used to easily make vertical scrollings.

Control Registers 26 and 27 (V9958 only)

These registers can be only written. Use the MSX-BASIC instruction VDP(27) or VDP(28) to access the corresponding register. The instruction reads the system variables REG26SAV (0FFFBh) or REG27SAV (0FFFCh) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#26: 0 0 HO8 HO7 HO6 HO5 HO4 HO3 (MSX2+/Turbo R)
R#27: 0 0 0 0 0 HO2 HO1 HO0 (MSX2+/Turbo R)
  • HO0-HO8 bits specify the vertical line number of the screen to place the left most (HO8 bit is only useful if SP2 of register 25 is 1. In screen 6 and 7, the scrolling will be every two lines.) (These two registers are initially reseted.)