VDP Mode Registers
This page was last modified 16:24, 10 August 2022 by Gdx. Based on work by Mars2000you and Aoineko and others.

Contents

Control Register 0 (All VDPs)

This register can be only written. Use the MSX-BASIC instruction VDP(0) to access it. The instruction reads the system variable REG0SAV (0F3DFh) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#0: 0 DG IE2 IE1 M5 M4 M3 EV (MSX1/2/2+/Turbo R)
  • DG specify the direction of the color bus. Write 1 to set the color bus as input in order to recover data in VRAM on MSX equipped with a digitizer. (V9938 & V9958 only)
  • IE2 enables (1) or disables (0) the light Pen interrupts. (Used only by Korean MSX2 Daewoo CPC-300 and CPC-400/400S, always reset it otherwise)
  • IE1 enables (1) or disables (0) the horizontal retrace interrupts indicated by the register 19. (V9938 & V9958 only)
  • M3-5 are bits are used with M1-2 bits of register 1 to define the VDP screen mode. (See here for detail)
  • EV is the bit to enable the external VDP input. (Disabled (0) by default, always 0 if V9938/58)

Control Register 1 (All VDPs)

This register can be only written. Use the MSX-BASIC instruction VDP(1) to access it. The instruction reads the system variable REG1SAV (0F3E0h) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#1: 4/16K BL IE0 M1 M2 0 SI MAG (MSX1/2/2+/Turbo R)
  • 4/16K selects VRAM configuration. Write 1 if the VDP is not a V9938 nor V9958.
  • BL disables the screen display when reset. VDP commands work a bit faster as well. Screen display is enabled by default.
  • IE0 enables (1) or disables (0) the vertical retrace interrupts that occur just after each display of the screen (foreground).
  • M1-2 are bits used with M3-5 bits of register 0 to define the VDP screen mode. (See here for details)
  • SI defines the sprite size. Write 1 to use 16x16 sprites, 0 to use 8x8 sprites.
  • MAG enlarges the sprites when 1 is written. (0 by default)

Control Register 8 (V9938/9958)

This register can be only written. Use the MSX-BASIC instruction VDP(9) to access it. The instruction reads the system variable REG9SAV (0FFE8h) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#8: MS LP TP CB VR 0 SPD BW (MSX2/2+/Turbo R)
  • MS serves to enable the mouse mode. (Not used on MSX computers, always reset it) (Does not exist on V9958.)
  • LP serves to enable the light pen. (Used only Korean MSX2 Daewoo CPC-300 and CPC-400 / 400S, set to 0 otherwise.) (Does not exist on V9958.)
  • TP must be 0 to make the color 0 transparent. On machines with video input, the image of the video signal received becomes visible instead of the color 0. When 1 these dots are black by default. The color can be changed by defining the palette. TP also affects sprites in the same way.
  • CB define the direction of the color bus. 1 for input, 0 for output (Default value).
  • VR defines the type of vram chips used. Write 1 if the VRAM is 64K x 1 bit or 64K x 4 bits, 0 if VRAM is 16K x 1 bit or 16K x 4 bits. This bit Affects how VDP performs refresh on DRAM chips.
  • SPD allows us to disable the sprites. The VDP commands work a little faster when the sprites are disabled (1). (Sprites are enabled by default)
  • BW defines the display to grayscale in 32 tones (1) or in colour. (0 by default)

Control Register 9 (V9938/9958)

This register can be only written. Use the MSX-BASIC instruction VDP(10) to access it. The instruction reads the system variable REG10SAV (0FFE9h) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#9: LN 0 S1 S0 IL E0 NT DC (MSX2/2+/Turbo R)
  • LN defines the height of the screen. 1 for 212 lines, 0 for 192 (Default value).
  • S1-S0 bits select the mode used simultaneously
    00 = Foreground (Default value)
    01 = Digitizer or Superimposition device
    10 = external video.
  • IL must be set for displaying with interlaced lines.
    Bit 2 (E0) must also be set and the bits N15 and N16 of register 2 must indicate the even page to be interlaced with the following page. (0 by default)
  • EO bit is used to activate the display of an even and odd page alternately, 1 frame out of two, for the second period in SCREEN 5 to 12 modes. (For more details, see register 13.)
  • NT define the frames display frequency.
    Set it to refresh the display at 50 Hertz (for PAL and SECAM TVs). Otherwise, the refresh is done at 60 Hertz (for NTSC and PAL-M TVs).
  • DC is to define the direction of the signal dot clock.
    1 sets DLCLK pin as input, 0 as output.

Control Register 25 (V9958 only)

This register can be only written. Use the MSX-BASIC instruction VDP(26) to access it. The instruction reads the system variable REG26SAV (0FFFAh) to return the requested value.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R#25: 0 CMD VDS YAE YJK WTE MAK SP2 (MSX2+/Turbo R)
  • CMD enables the VDP commands for screens 0 to 4 when 1. Coordinates work like in SCREEN 8. This bit is reseted when the screen mode is changed. (0 by default)
  • VDS should always be to 0 because it determines the function of the VDP pin 8 which clocks the Z80A to 3.579545 MHz. If this bit is set the pin 8 becomes a VDS output.
  • YAE must set with the YJK bit to get the screen 10/11 mode instead of screen 8. This bit is ignored when the bit YJK is 0. (0 by default)
  • YJK must set and the YAE bit reset to get the screen 12 mode instead of screen 8. (0 by default)
  • WTE enables the WAIT function when set. (0 by default) (not used on MSX computers)
  • MAK allows to hide the first 8 vertical lines at left of screen (8 lines in screens 5, 8, 10 to 12 - 16 lines in screens 6 and 7) when set. (0 by default)
  • SP2 sets the horizontal scrolling of the screen on two pages when 1 (displayed page must be odd)
    When 0, the horizontal scrolling occurs on a single page (Default value).